| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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ON Semiconductor |
Dual Monostable Multivibrators a negative-transitiontriggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger i |
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ON Semiconductor |
Quad 2-Input NAND Gate Power Supply Current ICC Total, Output HIGH Total, Output LOW 1.6 4.4 mA VCC = MAX – 20 – 0.4 –100 0.5 20 V µA mA mA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 – 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed |
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ON Semiconductor |
BCD to 7-Segment Decoder/Driver ith a maximum reverse current of 250 µA. Indicator segments requiring up to 24 mA of current may be driven directly from the SN74LS47 high performance output transistors. Display patterns for BCD input counts above nine are unique symbols to authenti |
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ON Semiconductor |
Quad 2-Input NAND Gate |
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ON Semiconductor |
Quad 2-Input AND Gate Current ICC Total, Output HIGH Total, Output LOW 4.8 8.8 mA VCC = MAX – 20 – 0.4 –100 0.5 20 V µA mA mA mA IOL = 8.0 mA 0.4 Min 2.0 0.8 – 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Vol |
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Hitachi Semiconductor |
Quadruple 2-input Positive NOR Gates rty rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document |
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ON Semiconductor |
Dual Monostable Multivibrators a negative-transitiontriggered input and a positive-transition-triggered input either of which can be used as an inhibit input. Pulse triggering occurs at a voltage level and is not related to the transition time of the input pulse. Schmitt-trigger i |
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Fairchild Semiconductor |
Quad 2-Input OR Gate C Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not gu |
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ON Semiconductor |
LOW POWER SCHOTTKY ation of the SN74LS85 under all possible logic conditions. The upper 11 lines describe the normal operation under all conditions that will occur in a single device or in a series expansion scheme. The lower five lines describe the operation under abn |
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ON Semiconductor |
Hex Inverter 0.65 – 1.5 2.7 3.5 V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VOL Output LOW Voltage 0.25 0.4 0.35 0.5 V IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH V IOL = 8.0 mA per Truth Table IIH Inp |
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National Semiconductor |
Hex Inverters to a 125 C 54LS DM74LS 0 C to a 70 C Storage Temperature Range b 65 C to a 150 C Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The |
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Fairchild Semiconductor |
Low Voltage Octal Buffer/Line Driver ■ Input and output interface capability to systems at 5V VCC ■ Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH240), also available without bushold feature (74LVT240) ■ Live insertion/extraction perm |
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Hitachi Semiconductor |
Octal D-type Flip Flops with 3-state Outputs • • • • • • VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VOUT (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25 °C) Typical VOH undershoot > 2.0 V (@VCC = |
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Fairchild Semiconductor |
Quad 2-Input NOR Gate 50°C Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not |
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Hitachi Semiconductor |
Dual J-K Negative-edge-triggered Flip-Flops s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual prope |
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Fairchild Semiconductor |
4-Bit Magnitude Comparator s Typical power dissipation 52 mW s Typical delay (4-bit words) 24 ns Ordering Code: Order Number DM74LS85M DM74LS85N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Pl |
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NXP Semiconductors |
Dual inverting buffer/line driver I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8-B/JESD36 (2.7 V to 3.6 V |
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Hitachi Semiconductor |
Octal Bidirectional Transceivers • • • • • • VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All input outputs VI/O (Max.) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@V |
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Hitachi Semiconductor |
Synchronous Decade Counters s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual prope |
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Fairchild Semiconductor |
Synchronous 4-Bit Up/Down Counter s Counts binary s Single down/up count control line s Count enable control input s Ripple clock output for cascading s Asynchronously presettable with load control s Parallel outputs s Cascadable for n-bit applications s Average propagation delay 20 |
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Desde 2024. D4U Semiconductor.
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