| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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ON Semiconductor |
8-Bit Serial-Input/Serial or Parallel-Output Shift Register • Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requiremen |
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NXP Semiconductors |
Quad 2-input NOR gate and benefits Input levels: For 74HC02: CMOS level For 74HCT02: TTL level Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 |
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NXP Semiconductors |
Hex inverter and benefits Complies with JEDEC standard JESD7A Input levels: For 74HC04: CMOS level For 74HCT04: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 |
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Hitachi Semiconductor |
These devices each consist of four 2-input digital multiplexers with common select and strobe inputs • • • • • High Speed Operation: tpd (Data to Output) = 12 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = |
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Hitachi Semiconductor |
Octal D-type Transparent Latches(with inverted 3-state outputs) • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (Data to Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input |
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System Logic Semiconductor |
Dual 2-Bit Transparent Latch = latched data SLS System Logic Semiconductor SL74HC75 MAXIMUM RATINGS * Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC |
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ON Semiconductor |
Hex Schmitt-Trigger Inverter • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance With the JEDEC Stand |
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Hitachi Semiconductor |
Octal D-type Flip-Flops (with 3-state outputs) • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (D to Q, Q) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input |
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IK Semiconductor |
Phase-Locked Loop and maintains a 0 degree phase shift between SIGIN and COMPIN IN74HC4046AD SOIC signals (duty cycle is immaterial). The linear VCO produces an output TA = -55° to 125° C for all packages signal VCOOUT whose frequency is determined by the voltage of i |
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Toshiba Semiconductor |
8-Bit Shift Register/Latch • High speed: fmax = 55 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 15 LSTTL loads for QA to QH 10 LSTTL loads for QH’ • Symmetrical outp |
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Hitachi Semiconductor |
Octal Buffers/Line Drivers (with 3-state outputs) • • • • • • LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed Operation: tpd (A to Y) = 12 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Cur |
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Toshiba Semiconductor |
Quad 2-Input NAND Gate • High speed: tpd = 6 ns (typ.) at VCC = 5 V • Low power dissipation: ICC = 1 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) |
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NXP Semiconductors |
Quad 2-input AND gate and benefits Complies with JEDEC standard JESD7A Input levels: For 74HC08: CMOS level For 74HCT08: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 |
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ON Semiconductor |
Octal 3-State Noninverting Bus Transceiver http://onsemi.com MARKING DIAGRAMS 20 20 1 TSSOP−20 DT SUFFIX CASE 948E 1 HC 245 ALYW G G • • • • • • • • • Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Cu |
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National Semiconductor |
8-3 Line Priority Encoder Y Typical propagation delay 13 ns Y Wide supply voltage range 2V – 6V Connection Diagram Dual-In-Line Package Truth Table Order Number MM54HC148 or MM74HC148 TL F 9390 – 1 Inputs Outputs EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO HXXXXXXXX H H H H H |
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IK Semiconductor |
Triple 3-Input AND Gate ply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ± |
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ON Semiconductor |
Dual D Flip-Flop 14 1 http://onsemi.com MARKING DIAGRAMS 14 SOIC−14 D SUFFIX CASE 751A 1 HC74G AWLYWW • • • • • • • • • Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Curre |
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ON Semiconductor |
Analog Multiplexers/Demultiplexers • Injection Current Cross−Coupling Less than 1 mV/mA (See Figure 10) • Pin Compatible to HC405X and MC1405XB Devices • Power Supply Range (VCC − GND) = 2.0 to 6.0 V • In Compliance With the Requirements of JEDEC Standard No. 7 A • Chip Complexity: 15 |
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ON Semiconductor |
Octal 3-State Noninverting D Flip-Flop http://onsemi.com MARKING DIAGRAMS 20 20 1 TSSOP−20 DT SUFFIX CASE 948E 1 HC574 A L Y W G = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package HC 574 ALYW G G • • • • • • • • Output Drive Capability: 15 LSTTL Loads Out |
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ON Semiconductor |
Quad 2-Input AND Gate • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance With the JEDEC Stand |
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Desde 2024. D4U Semiconductor.
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