No. | parte # | Fabricante | Descripción | Hoja de Datos |
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National Semiconductor |
LVDS 24-Bit Color Flat Panel Display (FPD) Link 65 MHz |
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National Semiconductor |
Panel Timing Controller n FPD-Link System Interface utilizes Low Voltage Differential Signaling (LVDS). n System programmable via EEPROM n Suitable for notebook and monitor applications n 8-bit or 6-bit system interface n XGA or SVGA capable n Supports single or dual port c |
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National Semiconductor |
LVDS 18-Bit Color Flat Panel Display FPD Link n n n n n n n n n n n n n 20 to 65 MHz shift clk support Up to 171 Mbytes/s bandwidth Cable size is reduced to save cost 290 mV swing LVDS devices for low EMI Low power CMOS design ( < 550 mW typ) Power-down mode saves power ( < 0.25 mW) PLL requires |
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National Semiconductor |
LVDS 18-Bit Color Flat Panel Display FPD Link |
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National Semiconductor |
TFT-LCD Column Driver n RSDS (Reduced Swing Differential Signaling) data bus for low power, reduced EMI and small PCB foot print n 85MHz maximum operating frequency at VDD1=3.0V (70MHz at VDD1=2.7V) n Pin compatible with Samsung S6C0666 n Ideal for XGA and SXGA applicatio |
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National Semiconductor |
TFT-LCD Column Driver n RSDS (Reduced Swing Differential Signaling) data bus for low power, reduced EMI and small PCB foot print n 85MHz maximum operating frequency at VDD1=3.0V n RSDS pin location and RSDS Switch feature simplify PCB layout and improve EMI n Ideal for UX |
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National Semiconductor |
TFT-LCD Column Driver n Up to 65 MHz clock n Supports both XGA and SXGA timing n Supports notebook and monitor applications n Charge Conservation for low power consumption n 64 Gray levels per color (18-bit color) n Externally programmable 2.2 gamma characteristic n Suppo |
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National Semiconductor |
Panel Timing Controller n FPD-Link System |
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National Semiconductor |
Low Dynamic Power (SVGA) XGA/WXGA TFTLCD Timing Controller ■ Reduced Swing Differential Sign |
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National Semiconductor |
Panel Timing Controller n FPD-Link System Interface utilizes Low Voltage Differential Signaling (LVDS). n System programmable via EEPROM n Suitable for notebook and monitor applications n 8-bit or 6-bit system interface n XGA or SVGA capable n Supports single or dual port c |
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National Semiconductor |
Universal Interface XGA Panel Timing Controller with RSDS (Reduced Swing Differential Signaling) and FPD-Link n RSDS (Reduced Swing Differential Signaling) Column Driver bus for low power and reduced EMI n Drives RSDS Column Drivers at 130 Mb/s with a 65 MHz clock n 6- or 8-bit LVDS Video System Interface (FPD-Link) n 10 General Purpose Outputs for Column/Ro |
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National Semiconductor |
528-Ch Small Format a-Si AMLCD Controller / Column Driver n 241 Outputs Accommodates from 2 to 240 Rows with a dummy row n Bumped Flip Chip Packaging (45um Row Centers) n 4 Flexible mounting/scan options provide for symmetric display layout n Wide Supply input range of 2.85V to 5.5V for direct connection to |
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National Semiconductor |
5-43 MHz DC-Balanced 24-Bit FPD-Link Serializer/Deserializer pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are ran |
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National Semiconductor |
5-43 MHz DC-Balanced 24-Bit FPD-Link Serializer/Deserializer pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. Using National Semiconductor’s proprietary random lock, the Serializer’s parallel data are ran |
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National Semiconductor |
5 - 65 MHz 24-bit Color FPD-Link Serializer/Deserializer and receiver equalization. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking compatibility. The Des may be configured to generate Spread Spectrum Clock and Data on its pa |
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National Semiconductor |
Low Dynamic Power XGA/WXGATFT-LCD Timing Controller n Reduced Swing Differential Signaling (RSDS) digital bus reduces dynamic power, EMI and bus-width from the timing control |
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National Semiconductor |
Low Power/ Low EMI/ TFT-LCD Column Driver with RSDS Inputs/ 64 Grayshades/ and 384 Outputs for XGA/SXGA Applications n RSDS™ (Reduced Swing Differential Signaling) data bus for low power, reduced EMI and small PCB foot print n Up to 85MHz clock n Supports both XGA and SXGA timing n Supports notebook and monitor applications n Smart Charge Conservation for low power |
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National Semiconductor |
Low Power/ Low EMI/ TFT-LCD Column Driver with RSDS Inputs/ 64 Grayshades/ and 384 Outputs for XGA/SXGA Applications n RSDS™ (Reduced Swing Differential Signaling) data bus for low power, reduced EMI and small PCB foot print n Up to 85MHz clock n Supports both XGA and SXGA timing n Supports notebook and monitor applications n Smart Charge Conservation for low power |
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National Semiconductor |
LCD TV TFT-LCD Timing Controller with PPDS Interface independent column driver control, large panel sizes, and lower overall system cost. Panel timing and control parameters can be programmed into an internal ROM for production or changed using and external EEPROM for initial product development. Fea |
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National Semiconductor |
Low Dynamic Power (SVGA) XGA/WXGA TFT-LCD Timing Controller n Reduced Swing Differential Signalling (RSDS™) digital bus reduces dynamic power, EMI and bus width from the timing controller n LVDS single pixel input interface system n Input clock range from 40 MHz to 85 MHz n Drives RSDS™ Column Drivers at 170 |
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