No. | parte # | Fabricante | Descripción | Hoja de Datos |
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National Semiconductor |
Quiet Series Quad 2-Input AND Gate GTOTM output control and undershoot corrector in addition to a split ground bus for superior ACMOS performance Features Y ICC reduced by 50% Y Guaranteed simultaneous switching noise level and dynamic threshold performance Y Improved latch-up immuni |
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National Semiconductor |
16-Bit Transparent Latch n Separate control logic for each byte n 16-bit version of the ABT373 n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Guaranteed latch-up protection n Standard Microcir |
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National Semiconductor |
Octal D Flip-Flop G TO TM output control and undershoot corrector in addition to a split ground bus for superior performance. The ACTQ574 is functionally identical to the ACTQ374 but with different pin-out. Industry Part Number 54ACTQ574 NS Part Numbers 54ACTQ574DMQ |
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National Semiconductor |
Octal D-Type Flip-Flop n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n See ’ABT273 for master reset version n See ’ABT373 for transparent latch version n See ’ABT374 for TRI-STATE® version n Ou |
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National Semiconductor |
Quad 2-Input NAND Gate n ICC reduced by 50% n Outputs source/sink 24 mA n ’ACT00 has TTL-compatible inputs Logic Symbol IEEE/IEC Pin Names A n, B n On Description Inputs Outputs 10025701 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC 10 |
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National Semiconductor |
Dual 4-Bit Decade Counters Y Y Y Y Y Switching specifications at 50 pF Switching specifications guaranteed over full temperature and VCC range Advanced oxide-isolated ion-implanted Schottky TTL process Individual clocks for A and B flip-flops provide dual divide-by-2 and d |
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National Semiconductor |
Quiet Series Octal Buffer/Line Driver GTOTM output control and undershoot corrector in addition to a split ground bus for superior performance Features Y ICC and IOZ reduced by 50% Y Guaranteed simultaneous switching noise level and dynamic threshold performance Y Guaranteed pin-to-pin |
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National Semiconductor |
Octal D-Type Flip-Flop n Edge-triggered D-type inputs n Buffered positive edge-triggered clock n TRI-STATE outputs for bus-oriented applications n Output sink capability of 48 mA, source capability of 24 mA n Guaranteed multiple output switching specifications n Output sw |
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National Semiconductor |
16-Bit Buffer/Line Driver n Separate control logic for each nibble n 16-bit version of the ’ABT244 n Outputs sink capability of 48 mA, source capability of 24 mA Ordering Code: Military 54ABT16244W-QML Package Number WA48A 48-Lead Cerpack Package Description Logic Symbol C |
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National Semiconductor |
16-Bit D Flip-Flop Separate control logic for each byte 16-bit version of the ABT374 Edge-triggered D-type inputs Buffered Positive edge-triggered clock High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion c |
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National Semiconductor |
OCTAL BUFFER AND LINE DRIVER Page Processing MIL-STD-883, Method 5004 Subgrp Description 1 2 3 4 5 6 7 8A 8B 9 10 11 Static tests at Static tests at Static tests at Dynamic tests at Dynamic tests at Dynamic tests at Functional tests at Functional tests at Functional tests at S |
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National Semiconductor |
Synchronous Presettable Binary Counter n ICC reduced by 50% Logic Symbols Pin Names CEP CET CP SR P0 –P3 PE Q0 –Q3 DS100275-1 Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Synchronous Reset Input Parallel Data Inputs Parallel Enable Input Flip-Flop |
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National Semiconductor |
Dual 4-Input NAND Gate n ICC reduced by 50% Logic Symbol IEEE/IEC DS100264-1 Pin Names An, Bn, Cn, Dn On Inputs Description Outputs Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100264-3 DS100264-2 FACT™ is a trademark of Fairchild |
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National Semiconductor |
Octal Buffer/Line Driver n ICC and IOZ reduced by 50% Logic Symbol Connection Diagrams Pin Assignment for DIP and Flatpak DS100281-1 DS100281-2 Pin Names OE1, OE2 I0 –I7 O0 –O7 Description TRI-STATE Output Enable Input TRI-STATE Output Enable Input (Active HIGH) Inputs Ou |
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National Semiconductor |
16-Bit Transceiver/Register GTOTM output control and undershoot corrector for superior performance Features Y Utilizes NSC FACT Quiet Series technology Y Guaranteed simultaneous switching noise level and dynamic threshold performance Y Guarant |
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National Semiconductor |
18-Bit Universal Bus Transceivers n Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode n Flow-through architecture optimizes PCB layout n Guaranteed latch-up protection n High impedance glitch free bus loading during entire power up a |
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National Semiconductor |
16-Bit Transceivers/Registers n Independent registers for A and B buses n Multiplexed real-time and stored data n A and B output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up an |
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National Semiconductor |
Octal Buffer/Line Driver n Output sink capability of 48 mA, source capability of 24 mA Ordering Code Military 54ABT240J-QML 54ABT240W-QML 54ABT240E-QML Package Number J20A W20A E20A Package Description 20-Lead Ceramic Dual-In-Line 20-Lead Cerpack 20-Lead Ceramic Leadless Ch |
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National Semiconductor |
Octal Buffer/Line Driver n Non-inverting buffers n Output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Sta |
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National Semiconductor |
Octal Buffer/Line Driver n Non-inverting buffers n Output sink capability of 48 mA, source capability of 24 mA n Output switching specified for both 50 pF and 250 pF loads Ordering Code Military 54ABT244J-QML 54ABT244W-QML 54ABT244E-QML Package Number J20A W20A E20A 20-Lead |
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