| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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NXP Semiconductors |
Dual 14-bits ADC I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual channel 14-bit pipelined ADC core 3.3 V, 1.8 V single supplies Flexible input voltage range: 1 V (p-p) to 2 V (p-p) with 6 dB programmable fine gain I 2 configurable serial outputs I C |
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NXP Semiconductors |
8-bit universal analog-to-digital converter 8-bit resolution Operation between 2.7 V and 5.5 V Sampling rate up to 40 MHz DC sampling allowed High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) CMOS |
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NXP Semiconductors |
Single 8-bits ADC I I I I I I I I I I I I I I 8-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (7.8 effective bits at 4.43 MHz full-scale input at fclk |
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NXP Semiconductors |
Single 11-bit ADC and benefits SNR, 66.5 dBFS / SFDR, 86 dBc Sample rate up to 125 Msps Input bandwidth, 600 MHz Power dissipation, 840 mW including analog input buffer SPI Duty cycle stabilizer 11-bit pipelined ADC core Clock input divider by 2 for l |
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NXP Semiconductors |
Dual 14-bits ADC I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual channel 14-bit pipelined ADC core 3.3 V, 1.8 V single supplies Flexible input voltage range: 1 V (p-p) to 2 V (p-p) with 6 dB programmable fine gain I 2 configurable serial outputs I C |
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NXP Semiconductors |
Single 8-bits ADC I I I I I I I I I I I I I I 8-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (7.8 effective bits at 4.43 MHz full-scale input at fclk |
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NXP Semiconductors |
Single 8-bits ADC I I I I I I I I I I I I I I 8-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (7.8 effective bits at 4.43 MHz full-scale input at fclk |
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NXP Semiconductors |
Single 8-bit ADC 8-bit resolution High-speed sampling rate up to 250 MHz Maximum analog input frequency up to 560 MHz Programmable acquisition output clock (complete conversion signal) Differential analog input Integrated voltage regulator or external con |
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NXP Semiconductors |
Single 8-bit ADC 8-bit resolution High-speed sampling rate up to 250 MHz Maximum analog input frequency up to 560 MHz Programmable acquisition output clock (complete conversion signal) Differential analog input Integrated voltage regulator or external con |
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NXP Semiconductors |
Single 10-bits ADC I I I I I I I I I I I I I I I I 10-bit resolution Sampling rate up to 70 MHz −3 dB bandwidth of 245 MHz 5 V power supplies and 3.3 V output power supply Binary or two’s complement CMOS outputs In-range CMOS compatible output TTL and CMOS compatible s |
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NXP Semiconductors |
Single 10-bit ADC and benefits SNR, 62 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps 10-bit pipelined ADC core Clock input divider by 2 for less jitter contribution Single 3 V supply Flexible input voltage range: 1 V p-p to 2 V p-p CMOS or LVDS DDR digit |
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NXP Semiconductors |
Single 10-bit ADC and benefits SNR, 61.7 dBFS / SFDR, 86 dBc Sample rate up to 125 Msps Input bandwidth, 600 MHz Power dissipation, 635 mW at 80 Msps, including analog input buffer SPI Duty cycle stabilizer 10-bit pipelined ADC core Clock input divide |
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NXP Semiconductors |
(ADC1206S040 - ADC1206S070) Single 12 bits ADC I I I I I I I I I I I I I I I I 12-bit resolution Sampling rate up to 70 MHz −3 dB bandwidth of 245 MHz 5 V power supplies and 3.3 V output power supply Binary or twos complement CMOS outputs In-range CMOS compatible output TTL and CMOS compatible st |
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NXP Semiconductors |
Single 12-bit ADC and benefits SNR, 70 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps 12-bit pipelined ADC core Clock input divider by 2 for less jitter contribution Single 3 V supply Flexible input voltage range: 1 V p-p to 2 V p-p CMOS or LVDS DDR digit |
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NXP Semiconductors |
Dual 12-bit ADC and benefits SNR, 70 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps Clock input divider by 2 for less jitter contribution 3 V, 1.8 V single supplies Flexible input voltage range: 1 V to 2 V (peak-to-peak) Two configurable serial outputs |
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NXP Semiconductors |
(ADC1412D065 - ADC1412D125) Dual 14-bit ADC I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual-channel14-bit pipelined ADC core Single 3 V supply Flexible input voltage range: 1 V to 2 V (p-p) with 6 dB programmable fine gain I CMOS or LVDS DDR digital outputs I INL ±1 LSB, DNL |
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NXP Semiconductors |
Single 16-bit ADC and benefits SNR, 72.3 dBFS; SFDR, 88 dBc Sample rates up to 125 Msps Single channel, 16-bit pipelined ADC core 3 V, 1.8 V power supplies Flexible input voltage range: 1 V (p-p) to 2 V (p-p) Serial output Power-down mode and Sleep mode |
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NXP Semiconductors |
Dual 14-bits ADC I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual channel 14-bit pipelined ADC core 3.3 V, 1.8 V single supplies Flexible input voltage range: 1 V (p-p) to 2 V (p-p) with 6 dB programmable fine gain I 2 configurable serial outputs I C |
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NXP Semiconductors |
Dual 14-bits ADC I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual channel 14-bit pipelined ADC core 3.3 V, 1.8 V single supplies Flexible input voltage range: 1 V (p-p) to 2 V (p-p) with 6 dB programmable fine gain I 2 configurable serial outputs I C |
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NXP Semiconductors |
Single 10-bits ADC I I I I I I I I I I I I I I 10-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 MHz full-scale input at fclk |
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Desde 2024. D4U Semiconductor.
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