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NXP |
eDP to LVDS bridge and benefits 2.1 Device features Embedded microcontroller and on-chip Non-Volatile Memory (NVM) allow for flexibility in firmware updates LVDS panel power-up (/down) sequencing control Firmware controlled panel power-up (/down) sequence timing |
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NXP |
eDP to LVDS bridge |
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NXP Semiconductors |
High speed differential line driver s Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard s Low-Voltage Differential Signaling with output voltage of 350 mV across a 50 Ω load or 700 mV across a 100 Ω load s 200 ps maximum channel-to-channel output skew s 600 ps typical outp |
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NXP Semiconductors |
High speed differential line driver s Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard s Low-Voltage Differential Signaling with output voltage of 350 mV across a 100 Ω load s 300 ps maximum channel to channel output skew s 500 ps typical output voltage rise and fall time |
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NXP Semiconductors |
High speed differential line receiver s s s s s s s s s Meets or exceeds the requirements of ANSI TIA/EIA-644 Standard Designed for signaling rates of up to 400 Mbps Differential input thresholds of ±100 mV Power dissipation of 60 mW typical at 200 MHz Typical propagation delay of 2.6 ns |
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NXP |
USB PD TCPC PHY as defined in [3]. PTN5110 implements I2C-bus interface registers, finite state machines and control flow, etc. as defined in [3]. Please refer to [3] for description of I2C registers, control descriptions, flow diagrams, etc. PTN5110 provides the ma |
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NXP |
Enhanced performance HDMI/DVI level shifter and benefits 2.1 High-speed TMDS level shifting Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain current-steering differential output signals TMDS level shifting operation up t |
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NXP |
High-speed serial logic translators • Meets LVDS EIA-644 and PECL standards • 2 pin-for-pin replacement input/output choices: – LVDS in, PECL out (PTN3310) – PECL in, LVDS out (PTN3311) Figure 1 shows the High-Speed Serial Logic Translator Device in a typical high speed optical modul |
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NXP |
Enhanced Performance HDMI/DVI Level Shifter 2.1 High-speed TMDS level shifting I Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals I TMDS level shifting operation up to 2.5 Gbit/s |
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NXP |
Enhanced Performance HDMI/DVI Level Shifter 2.1 High-speed TMDS level shifting I Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals I TMDS level shifting operation up to 2.5 Gbit/s |
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NXP Semiconductors |
DVI and HDMI level shifter supporting both DVI and HDMI. A derivative, PTN3300A, is available that is identical to the PTN3300B except that the HPD_SOURCE_N output is the inverting function of input HPD_SINK, level shifted to 1.1 V. For a fully-featured HDMI/DVI level shifter |
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NXP |
2-lane DisplayPort To VGA Adapter and benefits 2.1 VESA-compliant DisplayPort v1.1a converter Main Link: 1-lane and 2-lane modes supported HBR (High Bit Rate) at 2.7 Gbit/s per lane RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane BER (Bit Error Rate) better than 109 Down-sp |
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NXP |
DisplayPort v1.2 combo redriver and benefits • Flexible Type-C USB/DP combo redriver supports four signaling combinations specified in USB Type-C and VESA DisplayPort Alt Mode Standards through either I2C slave interface or ternary GPIO pins – Mode 1: One USB 3.1 Gen 1 port only – |
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NXP |
2-lane DisplayPort to VGA adapter and benefits 2.1 VESA-compliant DisplayPort v1.1a converter Main Link: 1-lane and 2-lane modes supported HBR (High Bit Rate) at 2.7 Gbit/s per lane RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane BER (Bit Error Rate) better than 109 Down-sp |
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NXP |
Low power DisplayPort to VGA adapter and benefits 2.1 VESA-compliant DisplayPort converter Main Link: 1-lane and 2-lane modes supported HBR (High Bit Rate) at 2.7 Gbit/s per lane RBR (Reduced Bit Rate) at 1.62 Gbit/s per lane BER (Bit Error Rate) better than 109 DisplayPort L |
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NXP |
1:10 LVDS clock distribution device • 100 ps part-to-part skew • 35 ps output-to-output skew • Differential design • Meets LVDS specification for driver outputs and receiver inputs • Reference voltage available output VBB • Low voltage VCC range of +2.375 V to 2.625 V • High signallin |
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NXP |
High-speed serial logic translators • Meets LVDS EIA-644 and PECL standards • 2 pin-for-pin replacement input/output choices: – LVDS in, PECL out (PTN3310) – PECL in, LVDS out (PTN3311) Figure 1 shows the High-Speed Serial Logic Translator Device in a typical high speed optical modul |
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NXP |
HDMI/DVI Level Shifter supporting HDMI dongle detection and active DDC buffering. For HDMI dongles, support of HDMI dongle detection via the DDC channel is mandatory, hence HDMI dongle applications should enable this feature for correct operation in accordance with Display |
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NXP Semiconductors |
DVI/HDMI level shifter supporting DVI and HDMI. It is identical to the PTN3300B except that the HPD_SOURCE_N output is the logic inverse function of input HPD_SINK, level shifted to 1.1 V. For a fully-featured HDMI/DVI level shifter function that supports active buffering |
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NXP |
SuperSpeed active switch and benefits 2 bidirectional differential channel, 2 : 1 multiplex/demultiplexer switch, supports USB 3.1 Gen 1 specification (SuperSpeed only) Compliant to SuperSpeed USB 3.1 Gen 1 standard Pin out data flow matches USB Type-C connector pin as |
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Desde 2024. D4U Semiconductor.
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