No. | parte # | Fabricante | Descripción | Hoja de Datos |
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NXP |
i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Feature Quad symmetric Cortex-A53 processors: • 32 KB L1 Instruction Cache • 32 KB L1 Data Cache • Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture: • 1 MB unified L2 cache • Support L2 cache RAMs protection wit |
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NXP |
Applications Processors Feature Quad symmetric Cortex-A53 processors: • 32 KB L1 Instruction Cache • 32 KB L1 Data Cache • Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture: • 1 MB unified L2 cache • Support L2 cache RAMs protection wit |
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NXP |
RF LDMOS Wideband Integrated Power Amplifiers • Production Tested in a Symmetrical Doherty Configuration • 100% PAR Tested for Guaranteed Output Power Capability • Characterized with Series Equivalent Large--Signal Impedance Parameters and Common Source S--Parameters • On--Chip Matching (50 Ohm |
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NXP |
RF LDMOS Wideband Integrated Power Amplifiers • Production Tested in a Symmetrical Doherty Configuration • 100% PAR Tested for Guaranteed Output Power Capability • Characterized with Series Equivalent Large--Signal Impedance Parameters and Common Source S--Parameters • On--Chip Matching (50 Ohm |
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NXP |
Applications Processors Feature Quad symmetric Cortex-A53 processors: • 32 KB L1 Instruction Cache • 32 KB L1 Data Cache • Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture: • 1 MB unified L2 cache • Support L2 cache RAMs protection wit |
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