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NXP |
Safety power system basis chip with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2(12) and -5(13) standards. The LIN interface fulf |
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NXP |
Single Wire CAN Transceiver • Waveshaping for low Electromagnetic Interference (EMI) • Detects and automatically handles loss of ground • Worst-case Sleep mode current of only 60 μA • Current limit prevents damage due to bus shorts • Built-in thermal shutdown on bus output • Pr |
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NXP |
Isolated network high-speed transceiver and benefits • 2.0 Mbit/s isolated network communication rate • Dual SPI architecture for message confirmation • Robust conducted and radiated immunity with wake-up • 3.3 V and 5.0 V compatible logic thresholds • Low sleep mode current with automati |
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NXP |
Advanced IGBT/SiC gate driver and benefits This section summarizes the key features, safety features, and regulatory approvals. 3.1 Key features • SPI interface for safety monitoring, programmability and flexibility • Low propagation delay and minimal PWM distortion • Integrated |
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NXP |
Safety power system basis chip with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2(12) and -5(13) standards. The LIN interface fulf |
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NXP |
Low Power Narrowband FM IF |
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NXP |
Battery cell controller • 5.0 V ≤ VPWR ≤ 30 V operation, 40 V transient • 3 to 6 cells management • 0.8 mV total cell voltage measurement error • Isolated 2.0 Mbps differential communication or 4.0 Mbps SPI • Addressable on initialization • Synchronized cell voltage/current |
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NXP |
Safety power system basis chip with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2(12) and -5(13) standards. The LIN interface fulf |
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NXP |
Battery cell controller • 5.0 V ≤ VPWR ≤ 30 V operation, 40 V transient • 3 to 6 cells management • Isolated 2.0 Mbps differential communication or 4.0 Mbps SPI • Addressable on initialization • Synchronized cell voltage/current measurement with Coulomb count • Total stack |
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NXP |
Three phase field effect transistor predriver and benefits • Extended supply voltage operating range: 6.0 V to 60 V • Gate drive capability of 1.0 A to 2.5 A • Device protection against reverse charge-injection from CGD and CGS of external FETs • Includes a charge pump to support full FET drive |
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NXP |
5.0A H-Bridge with Load Current Feedback • Fully specified operation 5.0 V to 28 V • Limited operation with reduced performance up to 40 V • 120 mΩ RDS(ON) Typical H-Bridge MOSFETs • TTL/CMOS Compatible Inputs • PWM Frequencies up to 10 kHz • Active Current Limiting (Regulation) • Fault Sta |
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NXP |
Three phase field effect transistor pre-driver and benefits • Extended operating range from 6.0 V to 58 V covers 12 V and 42 V systems • Gate drive capability of 1.0 A to 2.5 A • Fully specified from 8.0 V to 40 V, covers 12 and 24 V automotive systems • Device protection against reverse charge-i |
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NXP |
Multiple Switch Detection Interface a 22-to-1 analog multiplexer for reading inputs as analog. The analog input signal is buffered and provided on the AMUX output pin for the MCU to read. The 34972 device has two modes of operation, Normal and Sleep. Normal mode allows programming of t |
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NXP |
Power-system with multiple fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in enhanced high-speed CAN interface fulfills the ISO11898-2 and -5 standards. The LIN i |
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NXP |
Safety power system basis chip with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2(12) and -5(13) standards. The LIN interface fulf |
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NXP |
Safety power system basis chip with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2(12) and -5(13) standards. The LIN interface fulf |
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NXP |
Safety power system basis chip with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2(12) and -5(13) standards. The LIN interface fulf |
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NXP |
Safety power system basis chip with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2(12) and -5(13) standards. The LIN interface fulf |
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NXP |
Safety power system basis chip with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2(12) and -5(13) standards. The LIN interface fulf |
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NXP |
Safety power system basis chip with two fail-safe outputs, becoming a full part of a safety oriented system partitioning, to reach a high integrity safety level (up to ASIL D). The built-in CAN FD interface fulfills the ISO 11898-2(12) and -5(13) standards. The LIN interface fulf |
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Desde 2024. D4U Semiconductor.
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