NXP MAC Hoja de datos

No.	parte #	Fabricante	Descripción
1	MAC97A8	NXP	4Q Triac and benefits • Direct interfacing to logic level ICs • Direct interfacing to low power gate drivers and microcontrollers • High blocking voltage capability • Planar passivated for voltage ruggedness and reliability • Triggering in all four quadrants
2	MAC223A6	NXP	4Q Triac and benefits • High blocking voltage capability • High noise immunity • Planar passivated for voltage ruggedness and reliability • Triggering in all four quadrants 3. Applications • General purpose motor controls • General purpose switching 4. Quick
3	MAC97A6	NXP	4Q Triac and benefits • Direct interfacing to logic level ICs • Direct interfacing to low power gate drivers and microcontrollers • High blocking voltage capability • Planar passivated for voltage ruggedness and reliability • Triggering in all four quadrants
4	TDA9815	NXP	Multistandard/MAC VIF-PLL with QSS-IF and dual FM-PLL/AM demodulator • 5 V supply voltage • Two switched VIF inputs, gain controlled wide band VIF-amplifier (AC-coupled) • True synchronous demodulation with active carrier regeneration (very linear demodulation, good intermodulation figures, reduced harmonics, excellen
5	PZ3032	NXP	32 macrocell CPLD • Industry’s first TotalCMOS™ PLD – both CMOS design and • Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed process technologies DESCRIPTION The PZ3032 CPLD (Complex Programmable Logic Device) is the first in a f
6	MMA7260QR2	NXP	Micromachined Accelerometer signal conditioning, a 1-pole low pass filter, temperature compensation and g-Select which allows for the selection among 4 sensitivities. Zero-g offset full scale span and filter cut-off are factory set and require no external devices. Includes a Sl
7	MMA7260QT	NXP	Micromachined Accelerometer signal conditioning, a 1-pole low pass filter, temperature compensation and g-Select which allows for the selection among 4 sensitivities. Zero-g offset full scale span and filter cut-off are factory set and require no external devices. Includes a Sl
8	PCD6001	NXP	Digital telephone answering machine chip APPLICATION SUMMARY Metalink emulation GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description Pin types FUNCTIONAL DESCRIPTION Architecture I/O summary Overview of functional description POWER SUPPLY, RESET
9	UBA1707	NXP	Cordless telephone / answering machine line interface Line interface • Low DC line voltage; operates down to 1.2 V (excluding polarity guard) • Voltage regulator with adjustable DC voltage • DC mask for voltage or current regulation (CTR 21) • Line current limitation for protection • Electronic hook swi
10	PZ5064	NXP	64 Macrpcell CPLD
11	PZ3064	NXP	64 macrocell CPLD • Industry’s first TotalCMOS™ PLD – both CMOS design and • Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed process technologies DESCRIPTION The PZ3064 CPLD (Complex Programmable Logic Device) is the second in a