NXP HEF Hoja de datos

No.	parte #	Fabricante	Descripción
1	HEF4526B	NXP	Programmable 4-bit binary down counter and benefits  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  Specified from 40 C to +85 C  Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering in
2	HEF4013B	NXP	Dual D-type flip-flop independent set direct (SD), clear direct (CD), clock inputs (CP) and outputs (O, O). Data is accepted when CP is LOW and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct
3	HEF4049B	NXP	HEX inverting buffers and benefits  Accepts input voltages in excess of the supply voltage  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  Specified from 40 C to +85 C  Complies with JEDEC standard
4	HEF40192B	NXP	4-bit up/down decade counter ly. The outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum count state of ‘9’, the next HIGH to LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW
5	HEF4521B	NXP	24-stage frequency divider and oscillator tly the HEF4521B will count up to 224 = 16777216. The counting advances on the HIGH to LOW transition of the clock (I2). The outputs of the last seven stages are available for additional flexibility. Fig.1 Functional diagram. FAMILY DATA, IDD LIMIT
6	HEF4011B	NXP	Quadruple 2-input NAND gate Quadruple 2-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On Output transition times HIGH to LOW 5 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPHL; tPLH SYMBOL T
7	HEF40162B	NXP	4-bit synchronous decade counter
8	HEF4047B	NXP	Monostable/astable multivibrator and benefits 2.1 General  Monostable (one-shot) or astable (free-running) operation  True and complemented buffered outputs  Only one external resistor and capacitor required NXP Semiconductors HEF4047B Monostable/astable multivibrator 2.2 Mono
9	HEF4066B	NXP	Quad single-pole single-throw analog switch l range. Fig.1 Functional diagram. Fig.2 Pinning diagram. PINNING HEF4066BP(N): 14-lead DIL; plastic (SOT27-1) HEF4066BD(F): 14-lead DIL; ceramic (cerdip) (SOT73)) HEF4066BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America
10	HEF4086B	NXP	4-wide 2-input AND-OR-invert gate SO; plastic (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram. PINNING I0 to I8 I9 O gate inputs gate input (active LOW) output (active LOW) FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2
11	HEF4737B	NXP	Quadruple static decade counters allows common busing of the outputs. The counters are supplied with asynchronous reset and preset to 19 999 facilities making them suitable for counter and time base applications. All carry signals are available except from the first decade. Schmitt-
12	HEF4001B	NXP	Quadruple 2-input NOR gate and benefits  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  Specified from 40 C to +125 C  Complies with JEDEC standard JESD 13-B  Inputs and outputs are protected against el
13	HEF4006B	NXP	18-stage static shift register DD) and all the data in each register are shifted one position to the right on the HIGH to LOW transition of CP. Fig.2 Pinning diagram. HEF4006BP(N): HEF4006BD(F): HEF4006BT(D): Fig.1 Functional diagram. 14-lead DIL; plastic (SOT27-1) 14-lead DIL;
14	HEF4011UB	NXP	Quadruple 2-input NAND gate s provide identical inputs. FAMILY DATA, IDD LIMITS category GATES See Family Specifications for VIH/VIL unbuffered stages January 1995 2 Philips Semiconductors Product speciﬁcation Quadruple 2-input NAND gate AC CHARACTERISTICS VSS = 0 V; Tamb
15	HEF40195B	NXP	4-bit universal shift register 195B MSI input. When PE is LOW, data are loaded into the register from P0 to P3 on the LOW to HIGH transition of CP. When PE is HIGH, data are shifted into the first register position from J and K and all the data in the register are shifted one posi
16	HEF4022B	NXP	4-stage divide-by-8 Johnson counter of the HEF4022B are: • High speed • Spike-free decoded outputs • Carry output for cascading HEF4022B MSI Figure 7 shows a technique for extending the number of decoded output states for the HEF4022B. Decoded outputs are sequential within each stage
17	HEF4052B	NXP	Dual 4-channel analogue multiplexer/demultiplexer and benefits  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  Specified from 40 C to +85 C and 40 C to +125 C  Complies with JEDEC standard JESD 13-B 3. Applications  Analog
18	HEF4060B	NXP	14-stage ripple-carry binary counter/divider and oscillator to O13 = LOW), independent of other input conditions. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.1 Functional diagram. PINNING MR RS RTC CTC O3 to O9 O11 to O13 master reset
19	HEF4508B	NXP	Dual 4-bit latch dance OFF-state regardless of other input conditions. This allows the outputs to interface directly with bus orientated systems. When EO is LOW the contents of the latches are available at the outputs. Fig.1 Functional diagram. FAMILY DATA, IDD LIM
20	HEF4520B	NXP	Dual binary counter (O0 to O3 = LOW) independent of CP0, CP1. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Fig.2 Pinning diagram. HEF4520BP(N): HEF4520BD(F): HEF4520BT(D): 16-lead DIL; plastic (SOT3