No. | parte # | Fabricante | Descripción | Hoja de Datos |
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NXP |
12-bit high-speed Analog-to-Digital Converter ADC • 12-bit resolution • Sampling rate up to 55 MHz • −3 dB bandwidth of 190 MHz • 5 V power supplies • Binary or twos-complement CMOS outputs • In-range CMOS-compatible output • TLL-CMOS compatible static digital inputs • 3 to 5 V CMOS-compatible digit |
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NXP |
10-bit high-speed low-power ADC with internal reference regulator • 10-bit resolution (binary or gray code) • Sampling rate up to 40 MHz (/4 version) Sampling rate up to 80 MHz (/8 version) • DC sampling allowed • One clock cycle conversion only • High signal-to-noise ratio over a large analog input frequency range |
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NXP |
CMOS 8-bit A/D converters VREF/2 9 D GND 10 • Compatible with most microprocessors • Differential inputs • 3-State outputs • Logic levels TTL and MOS compatible • Can be used with internal or external clock • Analog input range 0 V to VCC • Single 5 V supply • Guaranteed sp |
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NXP |
10-bit high-speed low-power ADC • 10-bit resolution (binary or gray code) • Sampling rate up to 60 MHz • DC sampling allowed • One clock cycle conversion only • High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 5 MHz full-scale input at fcl |
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NXP |
12-bit high-speed Analog-to-Digital Converter ADC • 12-bit resolution • Sampling rate up to 55 MHz • −3 dB bandwidth of 190 MHz • 5 V power supplies • Binary or twos-complement CMOS outputs • In-range CMOS-compatible output • TLL-CMOS compatible static digital inputs • 3 to 5 V CMOS-compatible digit |
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NXP Semiconductors |
Dual 14-bits ADC I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual channel 14-bit pipelined ADC core 3.3 V, 1.8 V single supplies Flexible input voltage range: 1 V (p-p) to 2 V (p-p) with 6 dB programmable fine gain I 2 configurable serial outputs I C |
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NXP Semiconductors |
8-bit universal analog-to-digital converter 8-bit resolution Operation between 2.7 V and 5.5 V Sampling rate up to 40 MHz DC sampling allowed High signal-to-noise ratio over a large analog input frequency range (7.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) CMOS |
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NXP Semiconductors |
Single 8-bits ADC I I I I I I I I I I I I I I 8-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (7.8 effective bits at 4.43 MHz full-scale input at fclk |
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NXP Semiconductors |
Single 11-bit ADC and benefits SNR, 66.5 dBFS / SFDR, 86 dBc Sample rate up to 125 Msps Input bandwidth, 600 MHz Power dissipation, 840 mW including analog input buffer SPI Duty cycle stabilizer 11-bit pipelined ADC core Clock input divider by 2 for l |
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NXP Semiconductors |
Dual 12-bit ADC and benefits SNR, 70 dBFS; SFDR, 86 dBc Sample rate up to 125 Msps Clock input divider by 2 for less jitter contribution 3 V, 1.8 V single supplies Flexible input voltage range: 1 V to 2 V (peak-to-peak) Two configurable serial outputs |
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NXP |
A/D converter GND • Built-in track-and-hold function • No missing codes • No external clocking • Single supply—5VDC • Easy interface to all microprocessors, or operates stand-alone • Latched 3-State outputs • Logic inputs and outputs meet both MOS and TTL voltag |
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NXP |
Triple high speed Analog-to-Digital Converter ADC • Triple 8-bit ADC • Sampling rate up to 100 MHz • IC controllable via a serial interface, which can be either I2C-bus or 3-wire, selected via a TTL input pin • IC analog voltage input from 0.4 to 1.2 V (p-p) to produce full-scale ADC input of 1 V (p |
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NXP |
10-bit high-speed low-power ADC with internal reference regulator • 10-bit resolution • Sampling rate up to 50 MHz • DC sampling allowed • One clock cycle conversion only • High signal-to-noise ratio over a large analog input frequency range (9.3 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) • No mi |
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NXP |
10-bit high-speed low-power ADC • 10-bit resolution • Sampling rate up to 50 MHz • DC sampling allowed • One clock cycle conversion only • High signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) • No mi |
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NXP |
10-bit high-speed Analog-to-Digital Converter ADC • 10-bit resolution • Sampling rate up to 55 MHz • −3 dB bandwidth of 200 MHz • 5 V power supplies • Binary or twos-complement CMOS outputs • In-range CMOS-compatible output • TLL- CMOS-compatible static digital inputs • 3 to 5 V CMOS-compatible digi |
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NXP Semiconductors |
Dual 14-bits ADC I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual channel 14-bit pipelined ADC core 3.3 V, 1.8 V single supplies Flexible input voltage range: 1 V (p-p) to 2 V (p-p) with 6 dB programmable fine gain I 2 configurable serial outputs I C |
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NXP Semiconductors |
Single 8-bits ADC I I I I I I I I I I I I I I 8-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (7.8 effective bits at 4.43 MHz full-scale input at fclk |
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NXP Semiconductors |
Single 8-bits ADC I I I I I I I I I I I I I I 8-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (7.8 effective bits at 4.43 MHz full-scale input at fclk |
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NXP Semiconductors |
Single 8-bit ADC 8-bit resolution High-speed sampling rate up to 250 MHz Maximum analog input frequency up to 560 MHz Programmable acquisition output clock (complete conversion signal) Differential analog input Integrated voltage regulator or external con |
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NXP Semiconductors |
Single 8-bit ADC 8-bit resolution High-speed sampling rate up to 250 MHz Maximum analog input frequency up to 560 MHz Programmable acquisition output clock (complete conversion signal) Differential analog input Integrated voltage regulator or external con |
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