No. | parte # | Fabricante | Descripción | Hoja de Datos |
---|---|---|---|---|
|
|
NXP |
TV VHF mixer/oscillator UHF preamplifier |
|
|
|
NXP |
EdgeLock Secure Authenticator and benefits 2.1 Key benefits • Plug & Trust for fast and easy design with dedicated product support package for authentication use cases • Easy integration with different MCU & MPU platforms and OSs (Linux, RTOS, Windows, Android, etc.) • Turnkey so |
|
|
|
NXP |
Home automation modem • Full digital carrier generation and shaping • Modulation/demodulation frequency set by clock adjustment, from microcontroller or on-chip oscillator • High clock rate of 6 bits D/A (Digital-to-Analog) converter for rejection of aliasing components • |
|
|
|
NXP |
Pager baseband controller ORDERING INFORMATION GENERAL DESCRIPTION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION General CPU timing Overview on the different clocks used within the PCA5007 Memory organization Addressing I/O facilities Timer/event counters I2C-bus serial I/O Se |
|
|
|
NXP |
Pager baseband controller ORDERING INFORMATION GENERAL DESCRIPTION BLOCK DIAGRAM PINNING INFORMATION FUNCTIONAL DESCRIPTION General CPU timing Overview on the different clocks used within the PCA5010 Memory organization Addressing I/O facilities Timer/event counters I2C-bus s |
|
|
|
NXP |
DECT baseband controllers of the: PCD5090/xxx; DSP-ROM, with external ROM PCA5097/xxx; DSP-ROM, with Field Electronically Erasable Programmable Read Only Memory (FEEPROM). PCD5090; PCA5097 • On-chip reference voltage FEATURES General • The PCx509x is designed for GAP-compli |
|
|
|
NXP |
Home automation modem and benefits Full digital carrier generation and shaping Modulation/demodulation frequency set by clock adjustment, from microcontroller or on-chip oscillator High clock rate of 6-bit D/A (Digital to Analog) converter for rejection of aliasing |
|
|
|
NXP |
1.3 GHz I2C-bus controlled low phase noise frequency synthesizer • Complete 1.3 GHz single chip system • Optimized for low phase noise • Selectable divide-by-two prescaler • Operation up to 1.3 GHz without divide-by-two prescaler • Selectable reference divider ratio • Compatible with UK-DTT (Digital Terrestrial Te |
|
|
|
NXP |
2.65 GHz bidirectional I2C-bus controlled synthesizer • Complete 2.65 GHz single-chip system • Low power 5 V, 60 mA • I2C-bus programming • In-lock flag • Varicap drive disable • Low radiation • 5-level Analog to Digital Converter (ADC) • Address selection for Picture-In-Picture (PIP), DBS tuner, etc. • |
|
|
|
NXP |
2.7 GHz I2C-bus controlled low phase noise frequency synthesizer • Complete 2.7 GHz single chip system • Optimized for low phase noise • Selectable divide-by-two prescaler • Operation up to 2.3 GHz without divide-by-two prescaler (satellite zero-IF applications) and up to 2.7 GHz with divide-by-two prescaler • Sel |
|
|
|
NXP |
2.7 GHz I2C-bus controlled low phase noise frequency synthesizer • Complete 2.7 GHz single chip system • Optimized for low phase noise • Selectable divide-by-two prescaler • Operation up to 2.7 GHz with and without divide-by-two prescaler • Selectable reference divider ratio • Compatible with UK-DTT (Digital Terre |
|