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NXP |
Quad 2-input NAND gate and benefits Input levels: For 74HC00: CMOS level For 74HCT00: TTL level Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 |
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NXP |
Hex inverting Schmitt trigger reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly ch |
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NXP Semiconductors |
Quad 2-input NOR gate and benefits Input levels: For 74HC02: CMOS level For 74HCT02: TTL level Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 |
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NXP Semiconductors |
Hex inverter and benefits Complies with JEDEC standard JESD7A Input levels: For 74HC04: CMOS level For 74HCT04: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 |
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NXP |
8-bit parallel-in/serial out shift register I Asynchronous 8-bit parallel load I Synchronous serial input I Complies with JEDEC standard no. 7A I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V I Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Ap |
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NXP |
Quad 2-input EXCLUSIVE-OR gate and benefits Input levels: For 74HC86: CMOS level For 74HCT86: TTL level Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 |
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NXP |
Octal bus transceiver |
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NXP Semiconductors |
Quad 2-input AND gate and benefits Complies with JEDEC standard JESD7A Input levels: For 74HC08: CMOS level For 74HCT08: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 |
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NXP |
12-stage binary ripple counter and benefits Complies with JEDEC standard no. 7A Input levels: For 74HC4040: CMOS level For 74HCT4040: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from |
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NXP |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently of cl |
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NXP |
Presettable synchronous 4-bit binary up/down counter |
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NXP |
Presettable synchronous 4-bit binary up/down counter and benefits Input levels: For 74HC193: CMOS level For 74HCT193: TTL level Synchronous reversible 4-bit binary counting Asynchronous parallel load Asynchronous reset Expandable without external logic Complies with JEDEC standard no. 7 |
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NXP Semiconductors |
14-stage binary ripple counter and benefits All active components on chip RC or crystal oscillator configuration Complies with JEDEC standard no. 7 A Input levels: For 74HC4060: CMOS level For 74HCT4060: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V M |
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NXP |
Dual 4-channel analog multiplexer/demultiplexer four independent inputs/outputs (nY0, nY1, nY2 and nY3) and a common input/output (nZ). A digital enable input (E) and two digital select inputs (S0 and S1) are common to both switches. When E is HIGH, the switches are turned off. Inputs include clam |
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NXP |
Octal buffer/line driver two output enables (OE1 and OE2). A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and b |
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NXP |
Octal D-type flip-flop a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-im |
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NXP |
Octal D-type flip-flop clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW on MR forces the outputs LOW independently |
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NXP |
Johnson decade counter and benefits Wide supply voltage range from 2.0 V to 6.0 V Input levels: For 74HC4017: CMOS level For 74HCT4017: TTL level Complies with JEDEC standard no. 7 A ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 2 |
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NXP Semiconductors |
Binary up/down counter • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4516 are high-speed Si-gate CMOS devices and are pin compatible with the “4516” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. The |
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NXP |
8-bit serial-in serial or parallel-out shift register a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is trans |
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Desde 2024. D4U Semiconductor.
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