| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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NXP |
16-bit dual supply translating transceiver and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range: 3 V port (VCC(A)): 1.5 V to 3.6 V 5 V port (VCC(B)): 1.5 V to 5.5 V CMOS low power consumption Direct interface with TTL levels Control i |
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NXP |
Data selector/multiplexer |
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NXP |
2.5V/3.3V 16-bit D-type transparent latch • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple VCC and ground pins for minimum noise and ground boun |
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NXP |
18-bit buffer/driver • Wide supply voltage range of 1.2V to 3.6V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • MULTIBYTETM flow-through standard pin-out architecture • Low indu |
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NXP |
Triple 3-Input AND gate = Pin 14 GND = Pin 7 6 8 11 8 SC00020 SC00021 LOGIC DIAGRAM 1A 1B 1C 2A 2B 2C 3A 3B VCC = Pin 14 GND = Pin 7 3C 1 2 13 3 4 5 9 10 11 12 1Y FUNCTION TABLE INPUTS nA H 6 2Y OUTPUT nB H X X L nY H L L H nB H X L X L X 8 X 3Y SC00022 H = High |
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NXP |
Octal transceiver • Octal bidirectional bus interface • 3-State buffer outputs sink 24mA and source 15mA • Outputs are placed in high impedance state during power-off conditions PIN CONFIGURATION T/R 1 A0 A1 A2 A3 2 3 4 5 6 7 8 9 20 VCC 19 OE 18 B0 17 B1 16 B2 15 B3 |
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NXP |
Quad buffer four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling one of the 3-state outputs. 2. Features and benefits Quad bus interface 3-state buffers Live insertion and extraction permitted Output capability: HIGH 32 mA; LOW +64 mA Pow |
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NXP |
Octal bus transceiver/register |
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NXP |
Octal D-type flip-flop allow the use of these devices as translators in mixed 3.3 V or 5 V applications. The 74LVC574A is functionally identical to the 74LVC374A, but has a different pin arrangement. 2. Features and benefits 5 V tolerant inputs for interfacing with 5 V l |
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NXP |
Dual D-type flip-flop DESCRIPTION 74LVC74A • Wide supply voltage range of 1.2 V to 3.6 V • In accordance with JEDEC standard no. 8-1A. • Inputs accept voltages up to 5.5 V • CMOS low power consumption • Direct interface with TTL levels • Output drive capability 50 W tra |
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NXP |
16-bit edge triggered D-type flip-flop • 5 volt tolerant inputs/outputs for interfacing with 5V logic • Wide supply voltage range of 1.2 V to 3.6 V • Complies with JEDEC standard no. 8-1A • CMOS low power consumption • MULTIBYTETM flow-through standard pin-out architecture • Low inductan |
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NXP |
Low-power configurable multiple function gate |
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NXP |
Low-power configurable multiple function gate |
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NXP |
Dual 2-input NAND gate and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Symmetrical output impedance High noise immunity ESD protection: MIL-STD-883, method 3015 excee |
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NXP |
Quad 2-input NAND gate • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • For AHC on |
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NXP |
Dual 2-to-4 line decoder/demultiplexer • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt trigger actions • Inputs accept voltages higher than VCC • For AHC on |
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NXP |
Quad 2-input multiplexer • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Multiple input enable for easy expansion • Ideal fo |
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NXP |
2-input OR gate • Symmetrical output impedance • High noise immunity • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V • Low power dissipation • Balanced propagation delays • Very small 5-pin package • Output capability: stand |
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NXP |
Octal bus transceiver • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have a Schmitt-trigger action • Inputs accepts voltages higher than VCC • For AHC |
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NXP |
2-input NAND gate • Symmetrical output impedance • High noise immunity • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V • Low power dissipation • Balanced propagation delays • Very small 5-pin package • Output capability: stand |
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Desde 2024. D4U Semiconductor.
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