No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Motorola |
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer n and computing applications • Pin and function compatible to MPC948 FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A Functional Description The MPC9448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. E |
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Motorola |
(MPC562 / MPC563 / MPC564) RISC MCU Including Peripheral Pin Multiplexing with Flash and Code Compression Options The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller family. As shown in the block diagram, they are composed of: • High performance CPU system — High performance core • Single issue integer core • Compatible with |
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Motorola |
LOW VOLTAGE PLL CLOCK DRIVER to aid in system debug and test. The PECL reference input pins can be interfaced to a test signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in a system functional debug mod |
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Motorola |
2.5V and 3.3V LVCMOS Clock Fanout Buffer • Configurable 10 outputs LVCMOS clock distribution buffer MPC9446 LOW VOLTAGE SINGLE OR DUAL SUPPLY 2.5V AND 3.3V LVCMOS CLOCK DISTRIBUTION BUFFER Freescale Semiconductor, Inc... • Compatible to single, dual and mixed 3.3V/2.5V voltage supply • |
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Motorola Semiconductor |
RISC Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3. Comparison with the MPC7447A, MPC7447, MPC7445, and MPC7441 . . . . . . . . . . . . . . . . . . . . . . .7 4. General Parameters . . . . . . . . . . . . . . . . . . . . . . |
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Motorola |
800 MHz Low Voltage PECL Clock Synthesizer • • • • • • • • • • • • • • • 50 MHz to 800 MHz1 synthesized clock output signal Differential PECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference clock inp |
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Motorola |
LOW VOLTAGE PLL CLOCK DRIVER an extensive level of frequency programmability between the 12 outputs as well as the input vs output relationships. Using the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs |
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Motorola |
LOW VOLTAGE PLL CLOCK DRIVER |
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Motorola Inc |
LOW VOLTAGE PLL CLOCK DRIVER make the MPC958 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will tristate the output buffers when driven “high”. The MPC958 is fully 3.3V c |
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Motorola |
MPC5200 Hardware Specifications .......................................1 Electrical and Thermal Characteristics..............................5 Package Description ..................60 System Design Information ........69 Ordering Information ..................74 Document Revision H |
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Motorola |
Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver • Fully Integrated PLL MPC99J93 Freescale Semiconductor, Inc... FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A • • • • • Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32--Lead LQFP Packaging Functional Desc |
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Motorola |
Hardware Specifications Section 3, “Maximum Tolerated Ratings” Section 4, “Thermal Characteristics” Section 5, “Power Dissipation” Section 6, “DC Characteristics” Section 7, “Thermal Calculation and Measurement” Section 8, “Layout Practices” Section 9, “Bus Signal Timing” |
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Motorola |
(MPC930 / MPC931) LOW VOLTAGE PLL CLOCK DRIVER for power conscious portable or “green” designs. The power down pin will seemlessly reduce all of the clock rates by one half so that the system will run at half the potential clock rate to extend battery life. The POWER_DN pin is synchronized intern |
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Motorola |
PowerPC 603e RISC Microprocessor Section 1.3, ÒGeneral ParametersÓ Section 1.4, ÒElectrical and Thermal CharacteristicsÓ Section 1.5, ÒPin AssignmentsÓ Section 1.6, ÒPinout ListingsÓ Section 1.7, ÒPackage DescriptionsÓ Section 1.8, ÒSystem Design InformationÓ Section 1.9, ÒOrdering |
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Motorola |
512KB and 1MB BurstRAM edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. Presence detect pins are available for auto configuration of the cache control. The module family pinout will support 5 V and 3.3 V components for a clear path |
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Motorola |
512KB and 1MB BurstRAM edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. Presence detect pins are available for auto configuration of the cache control. The module family pinout will support 5 V and 3.3 V components for a clear path |
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Motorola Semiconductor |
Microcontroller coupled with high performance CMOS technology to provide substantial 3.6 Voltage Regulator Controller (VRC) and Power-On Reset (POR) Electrical Specifications9 3.7 Power-Up/Down Sequencing . . . . . . . . . . . . . . . . 10 3.8 DC Electrical Specifi |
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Motorola Semiconductor |
PowerQUICC II Pro Integrated Host Processor Hardware Specifications Figure 1 shows the major functional units within the MPC8347EA. Security DUART Dual I2C Timers GPIO e300 Core Interrupt Controller 32KB D-Cache 32KB I-Cache DDR SDRAM Controller Local Bus High-Speed USB 2.0 Dual Role Host 10/100/1000 Ethernet |
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Motorola |
(Hardware Specifications) PCI Bridge/Memory Controller 3 Section 1.3, “General Parameters” 5 Section 1.4, “Electrical and Thermal Characteristics” 5 Section 1.5, “Pin Assignments” 15 Section 1.6, “Pinout Listings 16 Section 1.7, “Package Description” 20 Section 1.8, “System Design Informatio |
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Motorola Semiconductor |
KMPC8250ACZUMHB Section 1.2, “Electrical and Thermal Characteristics” Section 1.2.1, “DC Electrical Characteristics” Section 1.2.2, “Thermal Characteristics” Section 1.2.3, “Power Considerations” Section 1.2.4, “AC Electrical Characteristics” Section 1.3, “Clock Co |
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