| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Lattice Semiconductor |
Zero Delay And Fan-Out Buffer CleanClock™ PLL Ultra Low Period Jitter 2.5ps Ultra Low Phase Jitter 6.5ps Fully Integrated High-Performance PLL • • • • • Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks Int |
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Lattice Semiconductor |
In-System Programmable Power Supply ■ Monitor and Control Multiple Power Supplies • • • • Simultaneously monitors up to 12 power supplies Sequence controller for power-up conditions Provides eight output control signals Programmable digital and analog circuitry Application Block Diagr |
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Lattice Semiconductor |
In-System Programmable High Density PLD Functional Block Diagram OutputDISCALOLNTDIENVUIECDERoutingSPool Output Routing Pool • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — Wide Input Gating for Fa |
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Lattice Semiconductor |
In-System Programmable SuperFAST High Density PLD Functional Block Diagram • SUPERFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 I/O Pins, Eight Dedicated Inputs — 128 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address D |
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Lattice Semiconductor |
In-System Programmable Power Supply Monitoring and Margining Controller ■ Power Supply Margin and Trim Functions • • • • Trim and margin up to six power supplies Dynamic voltage control through I2C Four hardware selectable voltage profiles Independent Digital Closed-Loop Trim function for each output Application Block Di |
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Lattice Semiconductor |
In-System Programmable Generic Digital CrosspointTM • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — Three Device Options: 80 to 160 Programmable I/O Pins — “Any Input t |
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Lattice Semiconductor |
In-System Programmable High Density PLD • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random |
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Lattice Semiconductor |
In-System Programmable Generic Digital CrosspointTM • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — Three Device Options: 80 to 160 Programmable I/O Pins — “Any Input t |
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Lattice Semiconductor |
In-System Programmable Generic Digital CrosspointTM |
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Lattice Semiconductor |
In-System Programmable Generic Digital CrosspointTM • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — Three Device Options: 80 to 160 Programmable I/O Pins — “Any Input t |
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Lattice Semiconductor |
In-System Programmable Generic Digital CrosspointTM |
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Lattice Semiconductor |
In-System Programmable Zero-Delay ■ Four Operating Configurations • • • • Zero delay buffer Zero delay and non-zero delay buffer Dual non-zero delay buffer Non-zero delay buffer with output divider • Up to +/- 5ns skew range • Coarse and fine adjustment modes ■ Up to Three Clock Freq |
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Lattice Semiconductor |
In-System Programmable Power Supply ■ Power-Down Mode ICC < 10µA ■ Programmable Threshold Monitors • Simultaneously monitors up to six power supplies • Programmable analog trip points (1% step size; 192 steps) • Programmable glitch filter • Power-off detection (75mV) Application Block |
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Lattice Semiconductor |
In-System Programmable Power Supply Supervisor / Reset Generator and Sequencing Controller Monitor and Control Multiple Power Supplies • Simultaneously monitors up to 10 power supplies • Provides up to 14 output control signals • Programmable digital and analog circuitry Embedded PLD for Sequence Control • 24-macrocell CPLD implement |
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Lattice Semiconductor |
High-Density Programmable Logic • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Rando |
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Lattice Semiconductor |
in-system programmable Generic Digital SwitchTM • HIGH-SPEED SWITCH MATRIX — 7.5 ns Maximum Propagation Delay — Typical Icc = 25 mA — UltraMOS® Advanced CMOS Technology • FLEXIBLE I/O MACROCELL — Any I/O Pin Can be Input, Output, or Fixed TTL High or Low — Programmable Output Polarity — Multiple O |
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Lattice Semiconductor |
In-System Programmable Generic Digital CrosspointTM |
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Lattice Semiconductor |
In-System Programmable Generic Digital CrosspointTM • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — Three Device Options: 80 to 160 Programmable I/O Pins — “Any Input t |
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Lattice Semiconductor |
In-System Programmable Generic Digital CrosspointTM • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — Three Device Options: 80 to 160 Programmable I/O Pins — “Any Input t |
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Lattice Semiconductor |
In-System Programmable Generic Digital CrosspointTM • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — Three Device Options: 80 to 160 Programmable I/O Pins — “Any Input t |
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Desde 2024. D4U Semiconductor.
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