No. | parte # | Fabricante | Descripción | Hoja de Datos |
---|---|---|---|---|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
Lattice Semiconductor |
MachXO ■ Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds • SRAM and |
|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
Lattice Semiconductor |
3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs ■ High Performance ■ Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction (Tj) – Industrial: -40 to 105°C junction (Tj) – Extended: -40 to 130°C junction (Tj) • For AEC-Q100 compliant devices, refer to LA-ispMA |
|
|
|
Lattice Semiconductor |
LA-MachXO Automotive ■ Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds • SRAM and |
|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
Lattice Semiconductor |
LA-MachXO Automotive ■ Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds • SRAM and |
|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
Lattice Semiconductor |
3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs ■ High Performance ■ Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction (Tj) – Industrial: -40 to 105°C junction (Tj) – Extended: -40 to 130°C junction (Tj) • For AEC-Q100 compliant devices, refer to LA-ispMA |
|
|
|
Lattice Semiconductor |
3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs ■ High Performance ■ Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction (Tj) – Industrial: -40 to 105°C junction (Tj) – Extended: -40 to 130°C junction (Tj) • For AEC-Q100 compliant devices, refer to LA-ispMA |
|
|
|
Lattice Semiconductor |
3.3V/2.5V/1.8V In-System Programmable SuperFAST High Density PLDs ■ High Performance ■ Broad Device Offering • Multiple temperature range support – Commercial: 0 to 90°C junction (Tj) – Industrial: -40 to 105°C junction (Tj) – Extended: -40 to 130°C junction (Tj) • For AEC-Q100 compliant devices, refer to LA-ispMA |
|
|
|
Lattice Semiconductor |
1.8V In-System Programmable Ultra Low Power PLDs ■ High Performance • fMAX = 260MHz maximum operating frequency • tPD = 4.4ns propagation delay • Up to four global clock pins with programmable clock polarity control • Up to 80 PTs per output ■ Broad Device Offering • 32 to 256 macrocells • Multipl |
|
|
|
Lattice Semiconductor |
MachXO ■ Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds • SRAM and |
|
|
|
Lattice Semiconductor |
MachXO ■ Non-volatile, Infinitely Reconfigurable • Instant-on – powers up in microseconds • Single chip, no external configuration memory required • Excellent design security, no bit stream to intercept • Reconfigure SRAM based logic in milliseconds • SRAM and |
|