No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Intel |
Octal T1/E1/J1 Short Haul PCM Transceiver ■ ■ ■ ■ ■ ■ ■ Octal T1/E1/J1 Pulse-Code Modulation (PCM) Transceiver with Jitter Attenuation for use in both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications 16 fully-independent receiver/transmitters Support for E1 standards: — Exceeds ETSI ETS |
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Intel Corporation |
Single-Port 10/100 Mbps PHY Transceiver ■ ■ ■ ■ ■ 3.3V Operation IEEE 802.3-compliant 10BASE-T or 100BASE-TX with integrated filters Auto-negotiation and parallel detection MII interface with extended register capability Robust baseline wander correction ■ ■ ■ ■ ■ Carrier Sense Multipl |
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Intel |
Dual Speed Fast Ethernet PHY Transceiver ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DataShee DataSheet4U.com ■ ■ ■ 3.3V Operation. Low power consumption (300 mW typical). Low-power “Sleep” mode. 10BASE-T and 100BASE-TX using a single RJ-45 connection. Supports auto-negotiation and parallel detection. MII inter |
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Intel Corporation |
Octal E1 Line Interface Unit a differential data receiver architecture with high noise interference margin. The receivers use peak detection and a variable threshold for reliable data recovery down to 500 mV or up to 12 dB of cable attenuation. Each receiver incorporates an anal |
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Intel |
Dual Speed Fast Ethernet PHY Transceiver ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 3.3V Operation. Low power consumption (300 mW typical). Low-power “Sleep” mode. 10BASE-T and 100BASE-TX using a single RJ-45 connection. Supports auto-negotiation and parallel detection. MII interface with extended register capab |
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Intel Corporation |
(LXT974 / LXT975) Fast Ethernet 10/100 Quad Transceivers s s s s s s Four independent IEEE 802.3compliant 10BASE-T or 100BASETX ports in a single chip. 100BASE-FX fiber-optic capable. Standard CSMA/CD or full-duplex operation. Supports auto-negotiation and legacy systems without auto-negotiation capabil |
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Intel |
(LXT9883 / LXT9863) Advanced 10/100 Unmanaged Repeater and functionality in a six-port device. This data sheet uses the singular designation “LXT98x3” to refer to both devices. The LXT98x3 provides auto-negotiation with parallel detection for the PHY ports. The LXT98x3 provides two internal repeater stat |
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Intel |
(LXT9880 / LXT9860) Advanced 10/100 Repeater and functionality in a six-port device. This data sheet uses the singular designation “LXT98x0” to refer to both devices. The LXT98x0 provides auto-negotiation with parallel detection for the PHY ports. The LXT98x0 provides two internal repeater stat |
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Intel |
(LXT9880 / LXT9860) Advanced 10/100 Repeater and functionality in a six-port device. This data sheet uses the singular designation “LXT98x0” to refer to both devices. The LXT98x0 provides auto-negotiation with parallel detection for the PHY ports. The LXT98x0 provides two internal repeater stat |
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Intel |
Dual T1/E1 Line Interface Unit B8ZS/HDB3 encoders and decoders, and a constant low output impedance transmitter for high return loss. Transmit pulse shape is selectable for various line lengths and cable types. The LXT332 incorporates an advanced crystal-less digital jitter attenu |
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Intel |
Single-Port 10/100 Mbps PHY Transceiver ■ ■ ■ ■ ■ 3.3V Operation IEEE 802.3-compliant 10BASE-T or 100BASE-TX with integrated filters Auto-negotiation and parallel detection MII interface with extended register capability Robust baseline wander correction ■ RESET_L ADDR[1:0] MDIO MDC TX |
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Intel |
Single-Port 10/100 Mbps PHY Transceiver ■ ■ ■ ■ ■ ■ ■ 3.3 V Operation Low power consumption (300 mW typical) 10BASE-T and 100BASE-TX using a single RJ-45 connection IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters Auto-negotiation and parallel detection MII interf |
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Intel |
(HBLXT986xA / HBLXT988xA) Multi Port 10/100 Mbps Repeaters or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® LXT9883A/9863A/9880A/9860A Rep |
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Intel |
(HBLXT986xA / HBLXT988xA) Multi Port 10/100 Mbps Repeaters or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® LXT9883A/9863A/9880A/9860A Rep |
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Intel |
(HBLXT986xA / HBLXT988xA) Multi Port 10/100 Mbps Repeaters or instructions marked “reserved” or “undefined.” Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® LXT9883A/9863A/9880A/9860A Rep |
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Intel Corporation |
Advanced 8-Port 10/100 Mbps PHY Transceivers included in the LXT9785E transceiver. The LXT9785E is an enhanced version of the LXT9785 that detects Data Terminal Equipment (DTE) requiring power from the switch over a CAT5 cable. The system uses the information collected by the LXT97985E to apply |
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INTEL |
QUAD T1/E1/J1 Transceiver or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The LXT386 may contain design defects or |
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Intel Corporation |
T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation s s s s s s Fully integrated transceivers for Short-Haul T1 or E1 interfaces Crystal-less digital jitter attenuation — Select either transmit or receive path — No crystal or high speed external clock required Meet or exceed specifications in ANS |
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Intel Corporation |
E-Rate Multiplexer n Performs four-E1 to one-E2, or four-E2 to one-E3 multiplexing. Five ICs will implement a sixteen-E1 to one-E3 multiplexer. n Fully compliant with the G.742 and G.751 ITU recommendations. Fully compliant with G.703 when used with LXT305/332 Line Int |
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Intel Corporation |
Dual-Speed Fast Ethernet Transceiver s s s s s IEEE 802.3 Compliant: — 10BASE-T and 100BASE-TX using a single RJ-45 connection. — Supports auto-negotiation and parallel detection for legacy systems. — MII interface with extended register capability. Robust baseline wander correction p |
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