No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Fairchild Semiconductor |
Programmable Shunt Regulator • • • • Programmable Output Voltage to 36 Volts Low Dynamic Output Impedance 0.2Ω Typical Sink Current Capability of 1.0 to 100mA Equivalent Full-Range Temperature Coefficient of 50ppm/°C Typical • Temperature Compensated For Operation Over Full Rate |
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Integrated Circuit Systems |
Programmable System Frequency Generator • 2 - CPUs @2.5V • 1 - IOAPIC @ 2.5V • 13 - SDRAM @ 3.3V • 6 - PCI @3.3V, • 1 - 48MHz, @3.3V • 1 - 24MHz @ 3.3V • 2 - REF @3.3V, 14.318MHz. Features: • Programmable ouput frequency. • Programmable ouput rise/fall time. • Programmable PCI_F and PCICL |
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Fairchild |
Programmable Shunt Regulator • Programmable Output Voltage to 36 V • Low Dynamic Output Impedance: 0.2 Ω (Typical) • Sink Current Capability: 1.0 to 100 mA • Equivalent Full-Range Temperature Coefficient of 50 ppm/°C (Typical) • Temperature Compensated for Operation Over Full Ra |
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Integrated Circuit Systems |
User Programmable Differential Output Graphics Clock Generator • • • • • • Supports high-resolution graphics - CLK output to 180 MHz Eliminates need for multiple ECL output crystal oscillators Fully programmable synthesizer capability - not just a clock multiplier Available in 20-pin 300-mil wide body SOIC packa |
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Fairchild |
Programmable Shunt Regulator • Programmable Output Voltage to 36 V • Low Dynamic Output Impedance: 0.2 Ω (Typical) • Sink Current Capability: 1.0 to 100 mA • Equivalent Full-Range Temperature Coefficient of 50 ppm/°C (Typical) • Temperature Compensated for Operation Over Full Ra |
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Integrated Circuit Systems |
Programmable Timing Control Hub • 2 - Pair of differential CPU clocks @ 3.3V • 1 - Pair of differential push pull CPU_CS clocks @ 2.5V • 3 - AGP @ 3.3V • 9 - PCI @ 3.3V • 2 - IOAPIC @ 2.5V • 1 - 48MHz @ 3.3V fixed • 1 - 24_48MHz @ 3.3V • 1 - REF @ 3.3V, 14.318MHz Features/Benefits |
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Integrated Circuit Systems |
Programmable Timing Control Hub • 2 - CPUs @ 2.5V • 13 - SDRAM @ 3.3V • 3 - 3V66 @ 3.3V • 8 - PCI @3.3V • 1 - 24/48MHz@ 3.3V • 1 - 48MHz @ 3.3V fixed • 1 - REF @3.3V, 14.318MHz Features/Benefits: • Programmable output frequency. • Programmable output divider ratios. • Programmable |
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Integrated Circuit Systems |
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTHESIZER • Packaged in 20-pin SSOP (QSOP) • Highly accurate frequency generation • M/N Multiplier PLL: M = 1..2048, N = 1..1024 • Serially programmable: user determines the output frequency via a 3-wire interface • Spread Spectrum frequency modulation for re |
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Integrated Circuit Systems |
Programmable System Frequency Generator • 2 - CPUs @2.5V • 1 - IOAPIC @ 2.5V • 13 - SDRAM @ 3.3V • 6 - PCI @3.3V, • 1 - 48MHz, @3.3V • 1 - 24MHz @ 3.3V • 2 - REF @3.3V, 14.318MHz. Features: • Programmable ouput frequency. • Programmable ouput rise/fall time. • Programmable PCICLK, PCICLK_ |
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Fairchild Semiconductor |
Programmable USB Type-C Controller Type-C Detection of Attach and Orientation Flexible Multi-Platform Support through I2C Programmability Supports: - Dual Role Port (DRP) - Downstream Facing Port (DFP) - Upstream Facing Port (UFP) - Accessory Modes - Alternate Interfaces Applica |
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Fairchild |
Programmable Shunt Regulator • Programmable Output Voltage to 36 V • Low Dynamic Output Impedance: 0.2 Ω (Typical) • Sink Current Capability: 1.0 to 100 mA • Equivalent Full-Range Temperature Coefficient of 50 ppm/°C (Typical) • Temperature Compensated for Operation Over Full Ra |
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Integrated Circuit Systems |
Programmable Timing Control Hub • 2 - CPU clocks @ 2.5V • 1 - Pairs of differential CPU clocks @ 3.3V • 7 - PCI including 1 free running @ 3.3V • 7 - SDRAM @ 3.3V • 1 - 48MHz @ 3.3V fixed • 1 - 24_48MHz selectable @ 3.3V • 2 - REF @ 3.3V, 14.318MHz Features/Benefits: • Programmabl |
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Integrated Circuit Systems |
User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator • Serial programming: Feedback and reference divisors, VCO gain, phase comparator gain, relative phase and test modes. Supports high-resolution graphics - Differential CLK out-puts to 230 MHz Eliminates need for multiple ECL output voltage controlled |
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Fairchild Semiconductor |
Digitally Programmable TinyBuck Regulator Fixed-Frequency Operation: 2.4 MHz Best-in-Class Load Transient Continuous Output Current Capability: 5 A Pulse Current Capability: 6.5 A (05 Option) 2.5 V to 5.5 V Input Voltage Range Digitally Programmable Output Voltage: - 00/01/03/05/ |
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Integrated Circuit Systems |
Programmable Timing Control Hub • 3 - Pairs of differential CPU clocks @ 3.3V • 3 - 3V66 @ 3.3V • 9 - PCI @ 3.3V • 2 - 48MHz @ 3.3V fixed • 1 - VCH/3V66 @ 3.3V, 48MHz or 66MHz • 1 - REF @ 3.3V, 14.318MHz Features/Benefits: • Programmable output frequency. • Programmable output div |
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Integrated Circuit Systems |
Quad PLL Field Programmable VersaClock Synthesizer include eight selectable configuration registers, up to two sets of four low-skew outputs. Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and |
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Fairchild Semiconductor |
Programmable Shunt Regulator • • • • Programmable Output Voltage to 36 Volts Low Dynamic Output Impedance 0.20 Typical Sink Current Capability of 1.0 to 100mA Equivalent Full-Range Temperature Coefficient of 50ppm/°C Typical • Temperature Compensated for Operation Over Full Rate |
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Fairchild |
PROGRAMMABLE TIMER/COUNTER devices. • ACCURATE TIMING FROM MICROSECONDS TO DAYS • PROGRAMMABLE DELAYS FROM 1 RC TO 255 RC • TIL, DTL AND CMOS COMPATIBLE OUTPUTS • TIMING DIRECTLY PROPORTIONAL TO RC TIME CONSTANT • HIGH ACCURACY - 0.5% • EXTERNAL SYNC AND MODULATION CAPABILIT |
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Fairchild |
Programmable Shunt Regulator • Programmable Output Voltage to 36 V • Low Dynamic Output Impedance 0.2 Ω (Typical) • Sink Current Capability: 1.0 to 100 mA • Equivalent Full-Range Temperature Coefficient of 50 ppm/°C (Typical) • Temperature Compensated for Operation Over Full Rat |
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Integrated Circuit Solution |
Field Programmable SS VersaClock Synthesizer include 4 selectable configuration registers. The device employs Phase-Locked Loop (PLL) techniques to run from a standard fundamental mode, inexpensive crystal, or clock. It can replace multiple crystals and oscillators, saving board space and cost. |
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