IK Semiconductor INA Hoja de datos

No.	parte #	Fabricante	Descripción
1	IN74ACT193	IK Semiconductor	4-Bit Synchronous Binary Up/Down Counter allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low
2	IW4516B	IK Semiconductor	Presettable Binary Up/Down Counter . This method provides a clean clock signal to the subsequent counting stage. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package
3	IN74HCT163A	IK Semiconductor	4-Bit Synchronous Binary Counter parallel Load, synchronous Reset, a Carry Output for cascading and count-enable controls. The IN74HCT163A is binary counter with synchronous Reset. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Vol
4	IW4029B	IK Semiconductor	Binary or BCD-Decade Counter the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY IN signal is low. The CARRY IN signal in the low state can thus be considered a CLOCK ENABLE. The CARRY IN terminal must be connected to GND
5	MICRF011	Micrel Semiconductor	QwikRadiotm Receiver/Data Demodulator Preliminary Information • • • • • • • • • • • • • • Complete UHF receiver on a monolithic chip Frequency range 300 to 440 MHz Typical range over 200 meters with monopole antenna Data rates to 2.5kbps (SWP), 10kbps (FIXED) Automatic tuning, no manual adjustment No Filters
6	IW4060B	IK Semiconductor	14-Bit Binary Divide/Counter NFORMATION IW4060BN Plastic IW4060BD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs Osc In Reset L L X H Outputs Q No change Advance to next state All Outputs are low w w w .d e e h s a t a . u t
7	INA3010	IK Semiconductor	Infrared Remote Control Transmitter ut data modulated with 1/2 the oscillator frequency at a 25% duty factor generated output information scan drivers ground (0V) scan drivers oscillator input test point 2 test point 1 sense inputs from key matrix voltage supply 8 DATA (OP3) 9-13 DR7-
8	MICRF002	Micrel Semiconductor	QwikRadiotm Low Power UHF Receiver Preliminary Information • 300MHz to 440MHz frequency range QwikRadio® The MICRF002 is a fully featured part in 16-pin packaging, the MICRF022 is the same part packaged in 8-pin packaging with a reduced feature set (see “Ordering Information” for more information). The MIC
9	INA2586	IK Semiconductor	1024 x 8 EEPROM . w w ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Non-volatile storage of information during 10 years Single supply (Ucc=4,75 B - 5,25 B) On-chip voltage multiplier On-chip generator of bulk biasing Serial input/output I2C-bus 10 000 ERASE/WRITE cycles per byte; Internal repr
10	IN74HC161A	IK Semiconductor	4-Bit Synchronous Binary Counter / Asychronous Reset parallel Load, asynchronous Reset, a Carry Output for cascading and count-enable controls. The IN74HC161A is binary counter with asynchronous Reset. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Inp
11	IN74HC163A	IK Semiconductor	4-Bit Synchronous Binary Counter / Sychronous Reset parallel Load, synchronous Reset, a Carry Output for cascading and count-enable controls. The IN74HC163A is binary counter with synchronous Reset. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input
12	IN74HC221A	IK Semiconductor	Dual Monostable Binary Up/Down Counter ORMATION IN74HC221AN Plastic IN74HC221AD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM 1A 1B 1RESET DEXT CEXT REXT CEXT DEXT REXT 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 V CC 1REXT/CEXT 1CEXT 1Q 2Q 2RESET 2B 2A 1Q 2Q 2CEX
13	IN74ACT161	IK Semiconductor	4-Bit Synchronous Binary Counter parallel Load, asynchronous Reset, a Carry Output for cascading and count-enable controls. The IN74ACT161 is binary counter with asynchronous Reset. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Vo
14	INA2586	IK Semiconductor	1Kx8 Static NMOS EEPROM IC Bus Interface . w w ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ Non-volatile storage of information during 10 years Single supply (Ucc=4,75 B - 5,25 B) On-chip voltage multiplier On-chip generator of bulk biasing Serial input/output I2C-bus 10 000 ERASE/WRITE cycles per byte; Internal repr
15	INA8583N	IK Semiconductor	Clock Calendar Table1 – PIN ASSIGNMENT OSCI OSCO A0 GND SDA SCL INT Vcc Pin 1 2 3 4 5 6 7 8 w w w t a .D OSCI OSCO A0 GND Generator input, 50Hz or occurrences Generator output Address input GND Data for I2C-bus Clock pulses for I2C-bus Open-drain interrupt o
16	IW4040B	IK Semiconductor	12-Bit Binary Counter ESET CLOCK Q1 PIN ASSIGNMENT FUNCTION TABLE Inputs Clock Reset L L X H= high level L = low level X=don’t care H Output Output state No change Advance to next state All Outputs are low RESET w w w .d h s a t a t e e . u 4 m o c 11 PIN 16 =
17	IN74AC163	IK Semiconductor	4-Bit Synchronous Binary Counter parallel Load, synchronous Reset, a Carry Output for cascading and count-enable controls. The IN74AC163 is binary counter with synchronous Reset. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input
18	IN74ACT163	IK Semiconductor	4-Bit Synchronous Binary Counter parallel Load, synchronous Reset, a Carry Output for cascading and count-enable controls. The IN74ACT163A is binary counter with synchronous Reset. • TTL/NMOS Compatible Input Levels • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Vol
19	IW4520B	IK Semiconductor	Dual Binary Up Counter IW4520BD SOIC TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs CLOCK ENABLE RESET H L X X L H X X X = don’t care L L L L L L H Outputs Mode Increment Counter Increment Counter No Change No Change No Change N
20	IN74HC193A	IK Semiconductor	4-Bit Synchronous Binary Up/Down Counter allows the counters to be used as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low