| No. | parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
|
|
|
IDT |
High Performance CMOS Bus Interface Latches • Equivalent to AM D's Am29841-46 Bipolar Registers in pinout/function, speeds and output drive over full temperature and voltage supply extremes • High-speed parallel latches -Noninverting transparent tpo = 5.5ns typo -Inverting transparent tpo = 6 |
|
|
|
|
Seme LAB |
CURRENT MODE REGULATING PULSE WIDTH MODULATORS • • • • • Guaranteed ±1% reference voltage tolerance Guaranteed ±10% frequency tolerance Low start –up current (<500 mA) Under voltage lockout with hysteresis Output state completely defined for all supply and input conditions • Interchangeable with U |
|
|
|
|
Seme LAB |
CURRENT MODE REGULATING PULSE WIDTH MODULATORS • • • • • • Guaranteed ±1% reference voltage tolerance Accurate oscillator discharge current Guaranteed ±10% frequency tolerance Low start –up current (<500 mA) Under voltage lockout with hysteresis Output state completely defined for all supply and i |
|
|
|
|
IDT |
Crystal-to-3.3V LVPECL Clock Synthesizer • One differential LVPECL output • Crystal oscillator interface designed for 18pF, 20MHz parallel resonant crystal • Cycle-to-Cycle Jitter: 14ps (maximum) • Period Jitter, RMS: 2.6ps (maximum) • Output Duty Cycle: 48 – 52% • Full 3.3V supply mode • 0 |
|
|
|
|
IDT |
Crystal-to-3.3V LVPECL Clock Synthesizer • One differential LVPECL output • Crystal oscillator interface designed for 18pF, 20MHz parallel resonant crystal • Cycle-to-Cycle Jitter: 14ps (maximum) • Period Jitter, RMS: 2.6ps (maximum) • Output Duty Cycle: 48 – 52% • Full 3.3V supply mode • 0 |
|
|
|
|
IDT |
8-output 3.3V LP-HCSL Zero-Delay Buffer ▪ Loss Of Signal (LOS) open drain output ▪ 8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs ▪ 9DBL0843 default Zout = 100Ω ▪ 9DBL0853 default Zout = 85Ω ▪ Easy AC-coupling to other logic families, see IDT application note AN-891. Key Specifications ▪ PCIe |
|
|
|
|
IDT |
NG Crystal-to-3.3V LVPECL Frequency Synthesizer • Fourth generation FemtoClock® Next Generation (NG) technology • One differential 3.3V LVPECL output and one LVCMOS/LVTTL output • Crystal oscillator interface designed for a 25MHz parallel resonant crystal • A 25MHz crystal |
|
|
|
|
Seme LAB |
CURRENT MODE REGULATING PULSE WIDTH MODULATORS • • • • • • Guaranteed ±1% reference voltage tolerance Accurate oscillator discharge current Guaranteed ±10% frequency tolerance Low start –up current (<500 mA) Under voltage lockout with hysteresis Output state completely defined for all supply and i |
|
|
|
|
IDT |
CRYSTAL-TOLVPECL/LVDS/LVCMOS CLOCK GENERATOR • Five banks of outputs: Bank A: one single-ended (QA0) LVCMOS output at: 133MHz and one (QA1/nQA1) LVPECL output at: 66.67MHz, 100MHz and 125MHz Bank B: two (QB0, QB1) LVCMOS outputs at: 50MHz Bank C: one (QC0/nQC0) differential LVPECL output at: 87 |
|
|
|
|
IDT |
CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER • One differential LVPECL output • Crystal oscillator interface designed for 18pF, 20MHz parallel resonant crystal • Cycle-to-Cycle Jitter: 25ps (maximum) • Period Jitter, RMS: 2ps (maximum) • Output Duty Cycle: 48 – 52% • Full 3.3V supply mode • 0°C |
|
|
|
|
IDT |
Crystal-to-LVPECL 133MHz Clock Synthesizer • Four LVPECL output pairs • Crystal oscillator interface: 25MHz • Differential PCLK/nPCLK input pair • PCLK/nPCLK supports the following input types: LVPECL, CML, SSTL • Output frequenc |
|
|
|
|
IDT |
CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER • One differential LVPECL output • Crystal oscillator interface designed for 18pF, 20MHz parallel resonant crystal • Cycle-to-Cycle Jitter: 25ps (maximum) • Period Jitter, RMS: 1.9ps (maximum) • Output Duty Cycle: 48 – 52% • Full 3.3V supply mode • 0 |
|
|
|
|
IDT |
Crystal-to-LVPECL Frequency Synthesizer • Fully integrated PLL, no external loop filter requirements • One differential 3.3V LVPECL output • Crystal oscillator interface: 10MHz to 25MHz • Output frequency range: 31.25MHz to 720MHz • VCO range: 250MHz to 720MHz • Parallel or serial interfac |
|
|
|
|
IDT |
Crystal-to-3.3V LVPECL Frequency Synthesizer W/Integrated Fanout Buffer • Six LVPECL outputs • Crystal oscillator interface • VCO range: 490MHz to 680MHz • Crystal input frequency range: 25MHz to 33.333MHz • RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz t |
|
|
|
|
IDT |
Crystal-to-3.3V Differential LVPECL Frequency • Fully integrated PLL, no external loop filter requirements • One differential 3.3V LVPECL output • Crystal oscillator interface: 10MHz to 25MHz • Output frequency range: 31.25MHz to 700MHz • VCO range: 250MHz to 700MHz • Parallel or serial interfac |
|
|
|
|
IDT |
NG Clock Synthesizer • Fourth generation FemtoClock® Next Generation (NG) technology • Seven single-ended LVCMOS outputs, 30 output impedance • Three LVPECL output pairs One differential LVPECL (QA, nQA) output pair: 156.25MHz Two selectable differential LVPECL output p |
|
|
|
|
Seme LAB |
CURRENT MODE REGULATING PULSE WIDTH MODULATORS • • • • • Guaranteed ±1% reference voltage tolerance Guaranteed ±10% frequency tolerance Low start –up current (<500 mA) Under voltage lockout with hysteresis Output state completely defined for all supply and input conditions • Interchangeable with U |
|
|
|
|
Seme LAB |
CURRENT MODE REGULATING PULSE WIDTH MODULATORS • • • • • • Guaranteed ±1% reference voltage tolerance Accurate oscillator discharge current Guaranteed ±10% frequency tolerance Low start –up current (<500 mA) Under voltage lockout with hysteresis Output state completely defined for all supply and i |
|
|
|
|
Seme LAB |
CURRENT MODE REGULATING PULSE WIDTH MODULATORS • • • • • Guaranteed ±1% reference voltage tolerance Guaranteed ±10% frequency tolerance Low start –up current (<500 mA) Under voltage lockout with hysteresis Output state completely defined for all supply and input conditions • Interchangeable with U |
|
Desde 2024. D4U Semiconductor.
|