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ICSI |
32K x 8 Low Power SRAM • Access time: 45, 70, 100 ns • Low active power: 70 mW • Low standby power — 60 µW CMOS standby • Fully static operation: no clock or refresh required • TTL compatible inputs and outputs • Single 3.3V power supply DESCRIPTION The ICSI IC62LV256 is |
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ULTRA LOW POWER CMOS STATIC RAM at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using Chip Enable Output and Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A |
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ICSI |
256K x 8 LOW POWER AND LOW Vcc CMOS STATIC RAM ipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC62LV2568L and IC62LV2568LL are |
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ICSI |
32K x 8 Low Power SRAM • High-speed access time: 15, 20, 25 ns • Automatic power-down when chip is deselected • CMOS low power operation — 255 mW (max.) operating — 0.18 mW (max.) CMOS standby • TTL compatible interface levels • Single 3.3V power supply • Fully static oper |
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ICSI |
512 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM • High-speed access times: 55, 70, 100 ns • CMOS low power operation ICC=18mA (typical)* operating ISB2=3µA (typical)* CMOS standby • TTL compatible interface levels • Single 2.7V-3.6V Vcc power supply • Fully static operation: no clock or refresh re |
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ICSI |
128K x 8 Ultra Low Power and Low VCC SRAM • Access times of 45, 55, and 70 ns • Low active power: 60 mW (typical) • Low standby power: 15 µW (typical) CMOS standby • Low data retention voltage: 2V (min.) • Available in Low Power (-L) and Ultra Low Power (-LL) • Output Enable (OE) and two Chi |
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ICSI |
256Kx16 bit Low Voltage and Ultra Low Power CMOS Static RAM • High-speed access times: 55, 70, 100 ns • CMOS low power operation -- 60 mW (typical) operating -- 3 µW (typical) CMOS standby • TTL compatible interface levels • Single 2.7V-3.6V Vcc power supply • Fully static operation: no clock or refresh requi |
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ICSI |
256Kx16 bit Low Voltage and Ultra Low Power CMOS Static RAM • High-speed access times: 55, 70, 100 ns • CMOS low power operation -- 60 mW (typical) operating -- 3 µW (typical) CMOS standby • TTL compatible interface levels • Single 2.7V-3.6V Vcc power supply • Fully static operation: no clock or refresh requi |
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ICSI |
256K x 8 LOW POWER AND LOW Vcc CMOS STATIC RAM ipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using two Chip Enable inputs, CE1 and CE2. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IC62LV2568L and IC62LV2568LL are |
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ICSI |
512 K x 16 bit Low Voltage and Ultra Low Power CMOS Static RAM • High-speed access times: 55, 70, 100 ns • CMOS low power operation ICC=18mA (typical)* operating ISB2=3µA (typical)* CMOS standby • TTL compatible interface levels • Single 2.7V-3.6V Vcc power supply • Fully static operation: no clock or refresh re |
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ICSI |
512K x 8 Hight Speed SRAM • High-speed access times: — 8, 10, 12 and 15 ns • High-preformance, lower-power CMOS process • Multiple center power and ground pins for greater noise immunity • Easy memory expansion with CE and OE options • CE power-down • Fully static operation: |
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ICSI |
128K x 16 Hight Speed SRAM • • • • • High-speed access time: 8, 10, 12, and 15 ns CMOS low power operation TTL and CMOS compatible interface levels Single 3.3V ± 10%power supply Fully static operation: no clock or refresh required • Three state outputs • Data control for upper |
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ICSI |
1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM • Access times of 55, 70, 100 ns • CMOS Low power operation: ICC=15mA (typical)* operation ISB2=2µA (typical)* standby • Low data retention voltage: 1.5V (min.) • Output Enable (OE) and Two Chip Enables (CE1, CE2) inputs for ease in applications • TT |
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ICSI |
1 M x 8 bit Low Voltage and Ultra Low Power CMOS Static RAM • Access times of 55, 70, 100 ns • CMOS Low power operation: ICC=15mA (typical)* operation ISB2=2µA (typical)* standby • Low data retention voltage: 1.5V (min.) • Output Enable (OE) and Two Chip Enables (CE1, CE2) inputs for ease in applications • TT |
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ICSI |
ULTRA LOW POWER CMOS STATIC RAM at which the power dissipation can be reduced by using CMOS input levels. Easy memory expansion is provided by using Chip Enable Output and Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A |
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ICSI |
512Kx8 bit Low Voltage and Ultra Low Power CMOS Static RAM • Access times of 55, 70, 100 ns • CMOS Low power operation: — 60 mW (typical) operation — 3 µW (typical) standby • Low data retention voltage: 1.5V (min.) • Output Enable (OE) and Chip Enable (CE) inputs for ease in applications • TTL compatible inp |
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ICSI |
128K x 8 Low Power CMOS SRAM • High-speed access time: 35, 45, 55, 70 ns • Low active power: 450 mW (typical) • Low standby power: 150 µW (typical) CMOS standby • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • Fully static operation: no cl |
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ICSI |
64K x 16 Hight Speed SRAM • High-speed access time: 8, 10, 12, and 15 ns • CMOS low power operation — 250 mW (typical) operating — 250 µW (typical) standby • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Th |
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ICSI |
32K x 8 Hight Speed SRAM • High-speed access times: -- 8, 10, 12, 15 ns • Automatic power-down when chip is deselected • CMOS low power operation -- 345 mW (max.) operating -- 7 mW (max.) CMOS standby • TTL compatible interface levels • Single 3.3V power supply • Fully stati |
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ICSI |
128K x 8 Ultra Low Power and Low VCC SRAM • Access times of 45, 55, and 70 ns • Low active power: 60 mW (typical) • Low standby power: 15 µW (typical) CMOS standby • Low data retention voltage: 2V (min.) • Available in Low Power (-L) and Ultra Low Power (-LL) • Output Enable (OE) and two Chi |
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Desde 2024. D4U Semiconductor.
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