No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Hynix Semiconductor |
Registered DDR SDRAM DIMM • • • • • • • 512MB (64M x 72) Registered DDR DIMM based on 64Mx4 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver to |
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Hynix Semiconductor |
Unbuffered DDR SO-DIMM • • • • • • 1GB (128M x 64) Unbuffered DDR SO-DIMM based on 128Mx8 DDR MCP SDRAM 200-pin small outline dual in-line memory module (SO-DIMM) 2.5V +/- 0.2V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface Fully diff |
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Hynix Semiconductor |
Low Profile Registered DDR SDRAM DIMM • • • • • • • 1GB (128M x 72) Low Profile Registered DDR DIMM based on stacked 128Mx4 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability Registered inputs with one-clock delay Phase-lock loop (P |
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Hynix Semiconductor |
240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version • JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver I |
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Hynix Semiconductor |
240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version • JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver I |
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Hynix Semiconductor |
PC100 SDRAM Unbuffered DIMM • • • • PC100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.25” (31.75mm) Height PCB with single sided components Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Inter |
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Hynix Semiconductor |
Unbuffered DDR SO-DIMM • • • • • • 128MB (16M x72) Unbuffered DDR SO-DIMM ECCbased on 16Mx16 DDR SDRAM JEDEC Standard 200-pin small outline dual in-line memory module (SO-DIMM) 2.5V +/- 0.2V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interf |
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Hynix Semiconductor |
Registered DDR SDRAM DIMM • • • • • • • 256MB (32M x 72) Registered DDR DIMM based on 32Mx8 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver to |
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Hynix Semiconductor |
240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version • JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver I |
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Hynix Semiconductor |
PC100 SDRAM Unbuffered DIMM • • • • PC100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.25” (31.75mm) Height PCB with double sided components Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Inter |
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Hynix Semiconductor |
Registered DDR SDRAM DIMM • • • • • • • 256MB (32M x 72) Registered DDR DIMM based on 32Mx8 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver to |
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Hynix Semiconductor |
Low Profile Registered DDR SDRAM DIMM • • • • • • • 1GB (128M x 72) Low Profile Registered DDR DIMM based on 64Mx8 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability Registered inputs with one-clock delay Phase-lock loop (PLL) clock |
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Hynix Semiconductor |
240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version • JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver I |
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Hynix Semiconductor |
240pin DDR2 SDRAM Unbuffered DIMMs based on 1Gb C version • JEDEC standard Double Data Rate2 Synchrnous DRAMs (DDR2 SDRAMs) with 1.8V +/ - 0.1V Power Supply All inputs and outputs are compatible with SSTL_1.8 interface 8 Bank architecture Posted CAS Programmable CAS Latency 3 ,4 ,5, 6 OCD (Off-Chip Driver I |
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Hynix Semiconductor |
32M x 64 bits Unbuffered DDR SDRAM DIMM • 256MB (32M x 64) Unbuffered DDR DIMM based on 16Mx8 DDR SDRAM • JEDEC Standard 184-pin dual in-line memory module (DIMM) • 2.5V +/- 0.2V VDD and VDDQ Power supply • All inputs and outputs are compatible with SSTL_2 interface • Fully differential cl |
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Hynix Semiconductor |
32M x 64 bits Unbuffered DDR SDRAM DIMM • 256MB (32M x 64) Unbuffered DDR DIMM based on 16Mx8 DDR SDRAM • JEDEC Standard 184-pin dual in-line memory module (DIMM) • 2.5V +/- 0.2V VDD and VDDQ Power supply • All inputs and outputs are compatible with SSTL_2 interface • Fully differential cl |
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Hynix Semiconductor |
1M X 9-Bit CMOS DRAM Module |
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Hynix Semiconductor |
PC133 SDRAM Unbuffered DIMM • • • • PC133/PC100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.25” (31.75mm) Height PCB with single sided components Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for |
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Hynix Semiconductor |
PC133 SDRAM Unbuffered DIMM • • • • PC133/PC100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.15” (29.21mm) Height PCB with single sided components Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for |
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Hynix Semiconductor |
PC100 SDRAM Unbuffered DIMM • • • • PC100MHz support 168pin SDRAM Unbuffered DIMM Serial Presence Detect with EEPROM 1.25” (31.75mm) Height PCB with single sided components Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface - 1, 2, 4 or 8 for Inter |
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