No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Hynix Semiconductor |
Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Ten Outputs No External RC Network |
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Hynix Semiconductor |
Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs N |
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Hynix Semiconductor |
Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Ten Outputs No External RC Network |
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Hynix Semiconductor |
Octal Noninverting 3-State Buffers |
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Hynix Semiconductor |
Octal Noninverting 3-State Transceivers |
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