No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Texas Instruments |
Digital Signal Processor General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The |
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Texas Instruments |
Digital Signal Processor for sharing global memory minimize unnecessary data transfers to take full advantage of the capabilities of the instruction set. FUNCTION A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Table 1. PGA/CLCC/LCCC Pin Assignments PIN K1/26 K2/28 L3/29 K3/30 L4/3 |
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Texas Instruments |
DIGITAL SIGNAL PROCESSOR General-purpose applications are enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, two external interface ports, two timers, two serial ports, and multiple interrupt structure. The SMJ320 |
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Texas Instruments |
MULTICHIP MODULE nal Buses Mapped to Memory -- 128K-Word × 32-Bit SRAM for Each C40 Local Bus (SMJ320MCM42D) -- 256K-Word × 32-Bit SRAM for Each C40 Local Bus (SMJ320MCM42C) D Ten External Communication Ports for Direct Processor-to-Processor Communication SMJ320MCM |
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Texas Instruments |
Digital Signal Processor − Hardware Support for IEEE Single-Precision Instructions − Hardware Support for IEEE Double-Precision Instructions − Byte-Addressable (8-, 16-, 32-Bit Data) − 32-Bit Address Range − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Cl |
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Texas Instruments |
Digital Signal Processor RS SGUS017H -- OCTOBER 1993 -- REVISED OCTOBER 2001 D IEEE Standard 1149.1† Test-Access Port (JTAG) D Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers: -- High Port-Data Rate of |
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Texas Instruments |
Digital Signal Processor of the communication ports are: D Six communication ports for direct interprocessor communication and processor I/O D 20 MBps bidirectional interface on each communication port for high-speed and low-cost multiprocessor interface D Separate input and |
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Texas Instruments |
Digital Signal Processor for sharing global memory minimize unnecessary data transfers to take full advantage of the capabilities of the instruction set. FUNCTION A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 Table 1. PGA/CLCC/LCCC Pin Assignments PIN K1/26 K2/28 L3/29 K3/30 L4/3 |
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Texas Instruments |
Digital Signal Processor 1 – Bit Counting •23456 Rad-Tolerant: 100-kRad (Si) TID • SEL Immune at 89MeV-cm2/mg LET Ions • QML-V Qualified, SMD 5962-98661 • Highest-Performance Floating-Point Digital Signal Processor (DSP) SMJ320C6701 – 7-ns Instruction Cycle Time – 140-MHz |
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Texas Instruments |
Digital Signal Processor − Byte-Addressable (8-/16-/32-/64-Bit Data) − 8-Bit Overflow Protection − Bit-Field Extract, Set, Clear − Normalization, Saturation, Bit-Counting − VelociTI.2 Increased Orthogonality D Host-Port Interface (HPI) − User-Configurable Bus Width (32-/16 |
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ETCTI |
SMx320VC33 Digital Signal Processor (Rev. F) |
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ETCTI |
SMJ320VC5416 Fixed-Point DSP (Rev. A) |
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ETCTI |
SMJ34020A Graphics System Processor (Rev. D) |
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Texas Instruments |
MULTICHIP MODULE nal Buses Mapped to Memory -- 128K-Word × 32-Bit SRAM for Each C40 Local Bus (SMJ320MCM42D) -- 256K-Word × 32-Bit SRAM for Each C40 Local Bus (SMJ320MCM42C) D Ten External Communication Ports for Direct Processor-to-Processor Communication SMJ320MCM |
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Texas Instruments |
Digital Signal Processor Features D High-Performance Static CMOS Technology D Three 32-Bit CPU-Timers − 150 MHz (6.67-ns Cycle Time) − Low-Power (1.8-V Core at 135 MHz, 1.9-V Core at 150 MHz, 3.3-V I/O) Design − 3.3-V Flash Voltage D JTAG Boundary Scan Support† D High-Pe |
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Texas Instruments |
DSP CONTROLLER rogrammable, Multiplexed I/O Pins D Phase-Locked-Loop (PLL)-Based Clock Module D Watchdog Timer Module (With Real-Time Interrupt) D Serial Communications Interface (SCI) Module D Serial Peripheral Interface (SPI) Module D Six External Interrupts (Pow |
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Texas Instruments |
Digital Signal Processor General-purpose applications are greatly enhanced by the large address space, multiprocessor interface, internally and externally generated wait states, one external interface port, two timers, one serial port, and multiple-interrupt structure. The |
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Texas Instruments |
Digital Signal Processor of the communication ports are: D Six communication ports for direct interprocessor communication and processor I/O D 20 MBps bidirectional interface on each communication port for high-speed and low-cost multiprocessor interface D Separate input and |
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Texas Instruments |
Digital Signal Processor (EPIC™) Technology Fabricated by Texas Instruments D Packaging -- 141-Pin Ceramic Grid Array (GFA Suffix) -- 132-Lead Ceramic Quad Flat Package (HFG Suffix) -- 132-Lead Plastic Quad Flat Package (PQ Suffix) SMJ320C50/SMQ320C50 DIGITAL SIGNAL PROCESS |
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Texas Instruments |
Digital Signal Processor − Byte-Addressable (8-/16-/32-/64-Bit Data) − 8-Bit Overflow Protection − Bit-Field Extract, Set, Clear − Normalization, Saturation, Bit-Counting − VelociTI.2 Increased Orthogonality D Host-Port Interface (HPI) − User-Configurable Bus Width (32-/16 |
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