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APOLLO MVP4 GH Added FP description, AC/DC tables, pin placement diagram; Fixed misc typos GH 7/298 Reconciled with target spec: changed pinouts & poweron config, added registers EC 7/27/98 Changed pinout; added pin descriptions; changed p/n to VT82C501; reforma |
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PCI INTEGRATED PERIPHERAL CONTROLLER 7HFKQRORJLHV ,QF :H &RQQHFW VT82C596A • Universal Serial Bus Controller − − − − − USB v.1.0 and Intel Universal HCI v.1.1 compatible Eighteen level (doublewords) data FIFO with full scatter and gather capability Root hub and two function ports |
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Real Time Clock • Drop-in replacement for IBM AT computer clock/calendar. • Pin configuration closely matches the DS12887, DS12885and DS12885Q • Counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year compensation • Binary or BCD |
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Clock Generator ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Generates essential clock signals for the motherboard 4V to 7V operating supply range Supports 80286, 80386 and 80486 based designs Wide range of selectable output frequencies < 2ns skew between CPU and 2X CPU clock outputs S |
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SOUTH BRIDGE PC99 COMPLIANT bullets, document title, and block diagram Replaced pinout diagram with blank BGA352 template Added LAN, LPC, and EEPROM pin descriptions, removed signals as req’d Updated Functions 5 and 6 per engineering input Added Preliminary Ballout & Mechanical |
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AMAZON PCI ETHERNET CONTROLLER * * * * PRELIMINARY VT86C926 * * * * * * * * * * * * Single chip Ethernet controller for PCI bus interface Software compatible to NE2000+, NE2000 Support 35ns access time SRAM Integrated 10BaseT TP interface -- Built-in pre-equalization circuit |
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APOLLO PRO-PLUS 7HFKQRORJLHV ,QF :H & &R RQQHFW VT82C693 • Full Featured Accelerated Graphics Port (AGP) Controller − Synchronous and pseudo-synchronous with the host CPU bus with optimal skew control PCI 33 MHz 33 MHz AGP CPU 66 MHz 100 MHz 66 MHz 66 MHz Mode |
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3.3-V 10-BIT ADDRESSABLE SCAN PORT MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (KTAG) TAP TRANSCEIVER |
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VT82C42 Keyboard Controller ∗ ∗ ∗ ∗ ∗ Fully hardware implemented, 0.8µm CMOS Technology. Very high speed response of A20 GATE & reset. Support PS2 style mouse. Compatible with all major BIOS, including AWARD, PHOENIX and AMI. 40 pin PDIP and 44 pin PLCC packages. 3. Function |
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MOBILE PCI INTEGRATED PERIPHERAL CONTROLLER 7HFKQRORJLHV ,QF :H &RQQHFW VT82C596A • Universal Serial Bus Controller − − − − − USB v.1.0 and Intel Universal HCI v.1.1 compatible Eighteen level (doublewords) data FIFO with full scatter and gather capability Root hub and two function ports |
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PCI INTEGRATED PERIPHERAL CONTROLLER bullets and overview - Added integrated APIC (changed H18, K18, J17 pin descriptions) - Added note to RTC CMOS Register Summary - Added / changed function 0 Rx42[6], Rx48[7-4], Rx5B[3], Rx5C[7-4, 2], Rx74[29-24, 8, 1], Rx87-89 - Added / changed funct |
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PCI SUPER-I/O INTEGRATED PERIPHERAL CONTROLLER bullets, pin typos, ROMCS# description, f0Rx8, f4Rx2 Fixed block diagram, pinouts, register descriptions and electrical specs Fixed GPIO, PCS/MCCS, DRQ/DACK#, DACK IRQ option, FDC on LPT Fixed SuperIO RxF0-1,F6; FDCIObase+1,Fn0Rx43,59,5B-C,68,74-7F,8 |
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EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTER (Rev. B) |
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EMBEDDED TEST-BUS CONTROLLERS IEEE STD 1149.1 (JTAG) TAP MASTER (Rev. B) |
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EMBEDDED TEST-BUS CONTROLLER IEEE STD 1149.1 (JTAG) TAP MASTERS (Rev. A) |
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PIC Integrated Peripheral Controller |
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PCI INTEGRATED PERIPHERAL CONTROLLER V RI 0LFURVRIW &RUS 3&,% LV D UHJLVWHUHG WUDGHPDUN RI WKH 3&, 6SHFLDO ,QWHUHVW *URXS 9(6$ LV D WUDGHPDUN RI WKH 9LGHR (OHFWURQLFV 6WDQGDUGV $VVRFLDWLRQ $OO WUDGHPDUNV DUH WKH SURSHUWLHV RI WKHLU UHVSHFWLYH RZQHUV 3HQWLXP3UR% *7/% DQG $3, |
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MOBILE PCI INTEGRATED PERIPHERAL CONTROLLER 7HFKQRORJLHV ,QF :H &RQQHFW VT82C596A • Universal Serial Bus Controller − − − − − USB v.1.0 and Intel Universal HCI v.1.1 compatible Eighteen level (doublewords) data FIFO with full scatter and gather capability Root hub and two function ports |
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ETCTI |
3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG (Rev. E) |
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3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG (Rev. E) |
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Desde 2024. D4U Semiconductor.
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