| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Texas Instruments |
DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS • Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard • Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz • Outputs Arranged in Pairs From Each Bank • |
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ETCTI |
MULTIPOINT-LVDS LINE DRIVER AND RECEIVER |
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Texas Instruments |
PLL FREQUENCY MULTIPLIER • A Member of the MuxIt™ SerializerDeserializer Building-Block Chip Family • Pin Selectable Frequency Multiplier Ratios Between 4 and 40 • Input Clock Frequencies From 5 to 50 MHz • Multiplied Clock Frequencies up to 400 MHz • Internal Loop Filters a |
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Texas Instruments |
Dual Pixel LVDS Display Interface 1 •2 Complies with OpenLDI Specification for Digital Display Interfaces • 32.5 to 112/170MHz Clock Support for DS90C387, 40 to 112MHz Clock Support for DS90CF388 • Supports SVGA through QXGA Panel Resolutions • Drives Long, Low Cost Cables • Up to 5. |
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Texas Instruments |
48-Bit LVDS 1 •2 Up to 5.38 Gbits/sec Bandwidth • 33 MHz to 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-emphasis Reduces Cable Loading Effects • DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion • C |
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Texas Instruments |
48-Bit LVDS 1 •2 Up to 5.38 Gbits/sec Bandwidth • 33 MHz to 112 MHz Input Clock Support • LVDS SER/DES Reduces Cable and Connector Size • Pre-emphasis Reduces Cable Loading Effects • DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion • C |
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Texas Instruments |
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS • Typically Meets or Exceeds ANSI TIA/EIA-644-1995 Standard • Operates From a Single 2.4-V to 3.6-V Supply • Signaling Rates up to 400 Mbit/s • Bus-Terminal ESD Exceeds 12 kV • Low-Voltage Differential Signaling With Typi- cal Output Voltages of 285 |
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Texas Instruments |
HIGH-SPEED DIFFERENTIAL RECEIVERS that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard providing a bet |
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Texas Instruments |
2:16 Low Additive Jitter LVDS Buffer 1 • 2:16 Differential Buffer • Low Additive Jitter: <300 fs RMS in 10 kHz to 20 MHz • Low Output Skew of 55 ps (Max) • Universal Inputs Accept LVDS, LVPECL, LVCMOS • Selectable Clock Inputs Through Control Pin • 16 LVDS Outputs, ANSI EIA/TIA-644A Sta |
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Texas Instruments |
2:8 Low Additive Jitter LVDS Buffer •1 2:8 Differential Buffer • Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz • Low Output Skew of 45 ps (Maximum) • Universal Inputs Accept LVDS, LVPECL, and LVCMOS • Selectable Clock Inputs Through Control Pin • 8 LVDS Outputs, ANSI EIA/TIA-64 |
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Texas Instruments |
LVDS 4x4 CROSSPOINT SWITCH • Greater Than 2.0 Gbps Operation • Nonblocking Architecture Allows Each Output to be Connected to Any Input • Pk-Pk Jitter: – 60 ps Typical at 2.0 Gbps – 110 ps Typical at 2.5 Gbps • Compatible With ANSI TIA/EIA-644-A LVDS Standard • Available Packa |
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Texas Instruments |
High-Speed Differential Line Receivers •1 Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Integrated 110-Ω Line Termination Resistors on LVDT Products • Designed for Signaling Rates Up to 250 Mbps • SN65 Versio |
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Texas Instruments |
LVDS QUAD DIFFERENTIAL LINE DRIVER • >400 Mbps (200 MHz) Signaling Rates • Flow-Through Pinout Simplifies PCB Layout • 50 ps Channel-to-Channel Skew (Typ) • 200 ps Differential Skew (Typ) • Propagation Delay Times 2.7 ns (Typ) • 3.3-V Power Supply Design • High Impedance LVDS Inputs o |
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Texas Instruments |
TRANSMITTERS 1 •23 21:3 Data Channel Compression at up to 163 Million Bytes per Second Throughput • Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI • 21 Data Channels Plus Clock-In Low-Voltage TTL and 3 Data Channels P |
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ETCTI |
SN65MLVD128/129 - 1:8 LVTTL to M-LVDS Repeater Dual 1:4 LVTTL to M-LVDS Repeate |
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Texas Instruments |
+3.3V Programmable LVDS Transmitter 1 •23 No Special Start-up Sequence Required Between Clock/Data and /PD Pins. Input Signal (Clock and Data) Can be Applied Either Before or After the Device is Powered. • Support Spread Spectrum Clocking Up to 100KHz Frequency Modulation & Deviations |
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Texas Instruments |
High-Speed Differential Line Drivers/Receivers • Meets or Exceeds the ANSI TIA/EIA-644 Standard • Designed for Signaling Rates 1 up to: – 630Mbps for Drivers – 400Mbps for Receivers • Operates From a 2.4V to 3.6V Supply • Available in SOT-23 and SOIC Packages • Bus-Terminal ESD Exceeds 9kV • Low- |
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Texas Instruments |
High-Speed Differential Line Drivers • Meet or Exceed the Requirements of ANSI TIA/ EIA-644 Standard • Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and 100-Ω Load • Typical Output Voltage Rise and Fall Times of 500 ps (400 Mbps) • Typical Propagation Delay Ti |
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Texas Instruments |
High-Speed Differential Line Receivers •1 Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Operate With a Single 3.3-V Supply • Designed for Signaling Rates of up to 150 Mbps (See ) • Differential Input Thresholds ±100 mV Max • Typical Propagation Delay Time of 2.1 ns • Powe |
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Texas Instruments |
High-Speed Differential Line Receivers •1 Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Integrated 110-Ω Line Termination Resistors on LVDT Products • Designed for Signaling Rates Up to 250 Mbps • SN65 Versio |
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Desde 2024. D4U Semiconductor.
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