| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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ETC |
STV2286 |
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Texas Instruments |
13-BIT TO 26-BIT REGISTERED BUFFER AND OUTPUTS SCES297D − FEBRUARY 2000 − REVISED AUGUST 2004 DGG PACKAGE (TOP VIEW) Q13A 1 Q12A 2 Q11A 3 Q10A 4 Q9A 5 VDDQ 6 GND 7 Q8A 8 Q7A 9 Q6A 10 Q5A 11 Q4A 12 Q3A 13 Q2A 14 GND 15 Q1A 16 Q13B 17 VDDQ 18 Q12B 19 Q11B 20 Q10B 21 Q9B 22 Q8B 23 Q7B 2 |
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ETC |
RGB HIGH VOLTAGE VIDEO AMPLIFIER |
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ETC |
STV5112 |
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Texas Instruments |
14-BIT REGISTERED BUFFER – REVISED APRIL 2003 DGG PACKAGE (TOP VIEW) Q1 1 Q2 2 GND 3 VDDQ 4 Q3 5 Q4 6 Q5 7 GND 8 VDDQ 9 Q6 10 Q7 11 VDDQ 12 GND 13 Q8 14 Q9 15 VDDQ 16 GND 17 Q10 18 Q11 19 Q12 20 VDDQ 21 GND 22 Q13 23 Q14 24 48 D1 47 D2 46 GND 45 VCC 44 D3 43 D4 42 D5 41 D |
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Texas Instruments |
26-BIT REGISTERED BUFFER • Controlled Baseline – One Assembly/Test Site, One Fabrication Site • Extended Temperature Performance of –40°C to 85°C • Enhanced Diminishing Manufacturing Sources (DMS) Support • Enhanced Product Change Notification • Qualification Pedigree (1) • |
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Texas Instruments |
24-Bit To 48-Bit Registered Buffer 1 •2 Controlled Baseline – One Assembly/Test Site, One Fabrication Site • Extended Temperature Performance of –40°C to 85°C • Enhanced Diminishing Manufacturing Sources (DMS) Support • Enhanced Product-Change Notification • Qualification Pedigree (1) |
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Texas Instruments |
24-BIT TO 48-BIT REGISTERED BUFFER 00-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) description/ordering information This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except t |
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Texas Instruments |
13-BIT TO 26-BIT REGISTERED BUFFER SN74SSTVF16859 13ĆBIT TO 26ĆBIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES429B − MARCH 2003 − REVISED FEBRUARY 2004 DGG PACKAGE (TOP VIEW) Q13A 1 Q12A 2 Q11A 3 Q10A 4 Q9A 5 VDDQ 6 GND 7 Q8A 8 Q7A 9 Q6A 10 Q5A 11 Q4A 12 Q3A 13 Q2A 14 GND |
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ETC |
STV2248 |
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Texas Instruments |
24-BIT TO 48-BIT REGISTERED BUFFER clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and |
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Desde 2024. D4U Semiconductor.
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