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ETC |
CERAMIC SURGE ABSORBERS |
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Texas Instruments |
4-Bit DRAM ICminer.com Electronic-Library Service CopyRight 2003 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Powered by ICminer.com Electronic-Library Service CopyRight 20 |
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ETC |
Block Diagram /50V 1kΩ 4.7Ω 0.1µF 4.7Ω /1W Ch3 OUT 4.7Ω /1W 3µH 4.7 3µH µ GND Ch2 OUT 4.7Ω /1W 0.1µF Ch1 OUT Ch1 IN 4.7Ω No.3 |
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ETC |
64Kb FRAM Serial Memory 64K bit Ferroelectric Nonvolatile RAM • Organized as 8,192 x 8 bits • High Endurance 1 Trillion (1012) Read/Writes • 10 Year Data Retention • NoDelay™ Writes • Advanced high-reliability ferroelectric process Very Fast Serial Peripheral Interface - SP |
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Texas Instruments |
Programmable NiCd/NiMH Fast-Charge Management 1 • Safe Management of Fast Charge for NiCd and NiMH Battery Packs • High-Frequency Switching Controller for Efficient and Simple Charger Design • Pre-Charge Qualification for Detecting Shorted, Damaged, or Overheated Cells • Fast-Charge Termination |
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Texas Instruments |
1:3 LVPECL CLOCK BUFFER + ADDITIONAL LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER • Distributes One Differential Clock Input to Three LVPECL Differential Clock Outputs and One LVCMOS Single-Ended Output • Programmable Output Divider for Two LVPECL Outputs and LVCMOS Output • Low-Output Skew 15 ps (Typical) for Clock-Distribution A |
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ETC |
STR-F6653 / STR-F6654 Block Diagram |
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ETC |
64-Bit RAM |
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Texas Instruments |
These programmable array logic high speed and a choice of either standard or half-power devices. They combine Advanced Low-Power Schottky technology with proven titanium-tungsten fuses. These devices will provide reliable, high-performance substitutes for conventional TTL logic. T |
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ETC |
MPEG IC Block Diagrams |
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ETC |
Deuterium-Filled Ceramic Thyratron eight . . . . Clearance required below mounting flange . . . Overall diameter (mounting flange) . . Net weight . . . . . Mounting position (see note Tube connections . . . . 212.7 mm (8.375 inches) max . . 57.15 mm (2.250 inches) min . 152.4 mm (6.00 |
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ETC |
DISC Ceramic Capacitors High discharge current capability up to 4000 Amps. Excellent clamping characteristics. Fast response time under 50 nanesesconds. Improve Product safety UL, CSA, VDE recognized special specification like a Automobile, Medical, Military, Aviation shoul |
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Texas Instruments |
256-BITS PROGRAMMABLE READ-ONLY MEMORIES 024 PACKAGING INFORMATION Orderable Device JBP18S030MJ Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) NRND CDIP J 16 25 Non-RoHS & Green Lead finish/ Ball material (6) SNPB MSL Peak Temp Op Temp (°C) (3) N / A f |
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ETC |
CMOS Programmable Electrically Erasable Logic Device s Multiple Speed Power, Temperature Options - VCC = 5 Volts ±10% - Speeds ranging from 5ns to 25 ns - Power as low as 37mA at 25MHz - Commercial and industrial versions available CMOS Electrically Erasable Technology - Superior factory testing - Rep |
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ETC |
CMOS Programmable Electrically Erasable Logic Device Ultra Low Power Operation - VCC = 5 Volts ±10% - Icc = 10 µA (typical) at standby - Icc = 2 mA (typical) at 1 MHz - tPD = 25ns. CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit an |
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ETC |
High-Speed Octal Programmable Timing Generator • 8 Fully Integrated Timing Generators for ATE Applications • 10/5ns Delay Range, 10ps Resolution • Fully Digital Interface. No Off-Chip DACs or Trim Components Required • ± 4 LSB Differential Non-Linearity High-Speed Octal Programmable Timing Gener |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
Block Diagram |
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Desde 2024. D4U Semiconductor.
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