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ETC |
Metallized polyester According to CECC 30401-042 / IEC 60384-2 / DIN 44122 0 7.5 10.0 15.0 22.5 27.5 37.5 p ± ± ± ± ± ± ± 0.4 0.4 0.4 0.4 0.4 0.4 0.5 d 0.5 0.6 0.6 0.8 0.8 0.8 1.0 std I max I 4+1 4+1 4+1 4+1 4+1 4+1 4+1 30 30 30 30 30 30 30 b ± 0.4 ± 0.4 ± 0.4 ± 0.4 ± 0.4 ± 0.4 ± 0.7 Capacitance tolerance Category temp |
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Texas Instruments |
14-OUT Network Synchronizer • Ultra-low jitter BAW VCO based Ethernet clocks – 42-fs typical/ 60-fs maximum RMS jitter at 312.5 MHz – 47-fs typical/ 65-fs maximum RMS jitter at 156.25 MHz • 3 high-performance Digital Phase Locked Loops (DPLLs) with paired Analog Phase Locked Lo |
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Texas Instruments |
Ultra-Low Jitter Network Synchronizer Clock • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) |
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ETC |
Magnetic Cylinder Switches 002 — 15.07.2002 ifm electronic gmbh Teichstra e 4 D-45 127 Essen file://E:\products\gb\ds\MK5002.htm m o .c U 4 t e e h S a at .D w w w 25/03/04 |
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Texas Instruments |
Ultra-Low Jitter Clock Synchronizer • BAW APLL with 40 fs RMS jitter at 491.52 MHz • Three high-performance digital phase locked loops (DPLLs) with paired analog phase locked loops (APLLs) – Programmable DPLL loop bandwidth from 0.01 Hz to 4 kHz – -116 dBc/Hz at 100 Hz offset at 122.88 |
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Desde 2024. D4U Semiconductor.
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