| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Texas Instruments |
Synchronous Up/Down Counters y counters. Presetting the counter to the number on preset data inputs (A−D) is accomplished by a low asynchronous parallel load (LOAD) input. Counting occurs when LOAD is high, count enable (CTEN) is low, and the down/up (D/U) input is either high f |
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Texas Instruments |
Octal D-Type EDGE-Triggered Flip-Flop 3-state outputs designed for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ′ACT11534 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q output |
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Texas Instruments |
8-Bit Binary Counter ual positive-edge triggered clocks. The function tables show the operation of the counter clock-enable (CCKEN, CCKEN) and output-enable (OE, OE) inputs. The counter input has direct load and clear functions. A low-going RCO pulse is obtained when the |
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Texas Instruments |
16-Bit Buffer/Drivers or one 16-bit buffer. These devices provide true outputs and complementary output-enable (OE and OE) inputs. 54ACT16241 . . . WD PACKAGE 74ACT16241 . . . DL PACKAGE (TOP VIEW) 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC |
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Texas Instruments |
16-BIT REGISTERED TRANSCEIVERS t control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data to B. If both CEAB and CLKAB are low, then B port will have the level of A port prior to the most recent low-to-high transit |
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Texas Instruments |
High-Speed CMOS Logic Presettable Counters • ’HC161, ’HCT161 4-Bit Binary Counter, Asynchronous Reset • ’HC163, ’HCT163 4-Bit Binary Counter, Synchronous Reset • Synchronous Counting and Loading • Two Count Enable Inputs for n-Bit Cascading • Look-Ahead Carry for High-Speed Counting • Fanout |
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Texas Instruments |
18-Bit Registered Transceivers • FCT-C speed at 4.6 ns • Ioff supports partial-power- mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages |
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Texas Instruments |
3-Line to 8-Line Decoder/DeMultiplexer to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This me |
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ETC |
5A Range AC Current Transformer Current Sensor are required. Specifications: Onboard precision micro current transformer. Onboard sampling resistor . Module can be measured within 5 a alternating current, the corresponding analog output 5 A/ 5 mA PCB board size: 18.3 (mm) x17 (mm). Rate |
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Texas Instruments |
20-Bit Latches • FCT-C speed at 5.5 ns (FCT16841T Com’l) • Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP ( |
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Texas Instruments |
18-Bit Registers • Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages • Industrial temper |
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Texas Instruments |
OCTAL BUFFER/LINE DRIVER nsmitters. Together with the ’ACT11240, this device provides the choice of various combinations of inverting and noninverting outputs. The 74ACT11244 is characterized for operation from −40°C to 85°C. FUNCTION TABLE OUTPUT ENABLE 1OE, 2OE DATA INP |
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Texas Instruments |
16-BIT D-TYPE TRANSPARENT LATCHES nal bus drivers, and working registers. These devices can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data (D) inputs if enable C is taken high. When C is taken low, the Q outputs are latched at the level |
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Texas Instruments |
18-BIT BUS-INTERFACE FLIP-FLOPS 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, parity bus interfacing, and working registers. The ’ACT16823 can |
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Texas Instruments |
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage D Buffered Inputs D Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumpt |
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Texas Instruments |
HEX D-TYPE FLIP-FLOP clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output |
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Texas Instruments |
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter will be dictated solely by the condit |
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Texas Instruments |
DUAL 4-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER s characterized for operation from – 40°C to 85°C. SELECT INPUTS BA XX LL LL LH LH HL HL HH HH FUNCTION TABLE (each multiplexer) DATA INPUTS STROBE OUTPUT C0 C1 C2 C3 OE Y XXXX H H LXXX L H HXXX L L XLXX L H XHXX L L XXLX L H |
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Texas Instruments |
Dual 1-of-4 Data Selectors/Multiplexers gates. Separate strobe inputs (G) are provided for each of the two four-line sections. 3 2 1 20 19 1C1 4 18 2C1 1C0 5 17 2C2 NC 6 16 NC A7 15 2C3 B8 14 2G 9 10 11 12 13 1Y GND NC 2Y 1G The 3-state outputs can interface with and drive d |
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Texas Instruments |
Quadruple Bus Buffer Gates • Inputs are TTL-voltage compatible • Latch-up performance exceeds 250mA per JESD 17 2 Applications • Enable or disable a digital signal • Controlling an indicator LED • Debounce a switch • Eliminate slow or noisy input signals 3 Description The ’A |
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Desde 2024. D4U Semiconductor.
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