| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Texas Instruments |
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the posit |
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Texas Instruments |
Quadruple 2-Input Positive-NOR Gates A NC 7 15 NC 2A 8 14 3Y 9 10 11 12 13 3B 3A NC GND 2B logic symbol† 2 1A ≥1 1 3 1Y 1B 5 2A 4 6 2Y 2B 8 3A 10 9 3Y 3B 11 4A 13 12 4Y 4B † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication |
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Texas Instruments |
Octal D-Type EDGE-Triggered Flip-Flop 3-state outputs designed for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the ′ACT11534 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q output |
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ETC |
Data Travo Flyback |
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Texas Instruments |
32-Bit Dual-Supply Bus Transceiver • Member of the Texas Instruments Widebus+™ Family • Control Inputs VIH/VIL Levels Referenced to VCCA Voltage • VCC Isolation Feature – If Either VCC Input is at GND, Both Ports are in the High-Impedance State • Overvoltage-Tolerant Inputs/Outputs Al |
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Texas Instruments |
SCAN TEST DEVICES ndom Pattern Generation From Outputs – Sample Inputs/Toggle Outputs – Binary Count From Outputs – Device Identification – Even-Parity Opcodes D Packaged in 64-Pin Plastic Thin Quad Flat (PM) Packages Using 0.5-mm Center-to-Center Spacings and 68-Pin |
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Texas Instruments |
OCTAL BUFFERS/LINE DRIVERS a high fan-out. The 54AC11241 is characterized for operation over the full military temperature range of – 55°C to 125°C. The 74AC11241 is characterized for operation from – 40°C to 85°C. 54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE |
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Texas Instruments |
8-Bit Binary Counter ual positive-edge triggered clocks. The function tables show the operation of the counter clock-enable (CCKEN, CCKEN) and output-enable (OE, OE) inputs. The counter input has direct load and clear functions. A low-going RCO pulse is obtained when the |
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Texas Instruments |
Hex Drivers 8 6Y NC 5 17 NC 2Y 6 16 5A NC 7 15 NC 3A 8 14 5Y 9 10 11 12 13 4A NC − No internal connection logic symbol† logic diagram (positive logic) 1 1A 3 2A 5 3A 9 4A 11 5A 13 6A 2 1Y 4 2Y 6 3Y 8 4Y 10 5Y 12 6Y † This symbol is in accordance |
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Texas Instruments |
16-BIT BUFFERS/DRIVERS tive-low output-enable (OE) inputs. SN54ABT162244 . . . WD PACKAGE SN74ABT162244 . . . DGG, DGV, OR DL PACKAGE (TOP VIEW) 1OE 1 1Y1 2 1Y2 3 GND 4 1Y3 5 1Y4 6 VCC 7 2Y1 8 2Y2 9 GND 10 2Y3 11 2Y4 12 3Y1 13 3Y2 14 GND 15 3Y3 16 3Y4 17 VCC 18 4Y1 19 4Y |
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Texas Instruments |
3-Line to 8-Line Decoder/DeMultiplexer to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than the typical access time of the memory. This me |
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Texas Instruments |
HEX INVERTER 1 • Operating Range 2-V to 5.5-V • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SN54AHC04 . . . JORWP ACKAGE |
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Texas Instruments |
OCTAL BUFFER/LINE DRIVER nsmitters. Together with the ’ACT11240, this device provides the choice of various combinations of inverting and noninverting outputs. The 74ACT11244 is characterized for operation from −40°C to 85°C. FUNCTION TABLE OUTPUT ENABLE 1OE, 2OE DATA INP |
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Texas Instruments |
18-BIT BUS-INTERFACE FLIP-FLOPS 3-state outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, parity bus interfacing, and working registers. The ’ACT16823 can |
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Texas Instruments |
18-BIT BUS TRANSCEIVERS om the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the output-enable (OEAB or OEBA) inputs. 54ACT16863 . . . WD PACKAGE 74ACT16863 . . . DL PACKAGE (TOP VIEW) 1OEAB 1 1B1 2 1B2 3 GND 4 1B3 5 1B4 6 VCC 7 1B5 8 |
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Texas Instruments |
OCTAL TRANSCEIVERS AND LINE/MOS DRIVERS or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated. A8 GND B8 SN54ABT2245 . . . J OR W PACKAGE S |
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Texas Instruments |
18-BIT UNIVERSAL BUS TRANSCEIVERS allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the |
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ETC |
Dual D Flip-Flop with Set and Reset High-Speed Silicon-Gate CMOS L H H H H L H Clock X X X Data X X X H L X X Outputs Q H L H * Q L H H* L H H L No Change No Change H H X No Change *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high |
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ETCTI |
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear And Preset (Rev. C) |
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Texas Instruments |
SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTER a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter will be dictated solely by the condit |
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Desde 2024. D4U Semiconductor.
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