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Texas Instruments |
4-Bit DRAM ICminer.com Electronic-Library Service CopyRight 2003 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Powered by ICminer.com Electronic-Library Service CopyRight 20 |
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ETC |
64Kb FRAM Serial Memory 64K bit Ferroelectric Nonvolatile RAM • Organized as 8,192 x 8 bits • High Endurance 1 Trillion (1012) Read/Writes • 10 Year Data Retention • NoDelay™ Writes • Advanced high-reliability ferroelectric process Very Fast Serial Peripheral Interface - SP |
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Texas Instruments |
2-A High Efficiency Synchronous Buck Converter •1 Up to 95% Efficiency • Low RDS(ON) Switches 100 mΩ / 60 mΩ • 2.5-V to 5.5-V Input Voltage Range • Adjustable Output Voltage from 0.6 V to VIN • Power Save Mode for Light Load Efficiency • 100% Duty Cycle for Lowest Dropout • 35-µA Operating Quiesc |
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Texas Instruments |
1-A High Efficiency Synchronous Buck Converter •1 Up to 95% Efficiency • Low RDS(ON) Switches 150 mΩ / 100 mΩ • 2.5-V to 5.5-V Input Voltage Range • Adjustable Output Voltage from 0.6 V to VIN • Power Save Mode for Light Load Efficiency • 100% Duty Cycle for Lowest Dropout • 35-µA Operating Quies |
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Texas Instruments |
256-BITS PROGRAMMABLE READ-ONLY MEMORIES 024 PACKAGING INFORMATION Orderable Device JBP18S030MJ Status Package Type Package Pins Package Eco Plan (1) Drawing Qty (2) NRND CDIP J 16 25 Non-RoHS & Green Lead finish/ Ball material (6) SNPB MSL Peak Temp Op Temp (°C) (3) N / A f |
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ETC |
FET |
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Texas Instruments |
8-BIT MICROCONTROLLER – Low-Power Modes: STANDBY and HALT – Commercial, Industrial, and Automotive Temperature Ranges – Clock Options – Divide-by-4 (0.5 MHz – 5 MHz SYSCLK) – Divide-by-1 (2 MHz – 5 MHz SYSCLK) Phase-Locked Loop (PLL) – Supply Voltage (VCC): 5 V ± 10% D Ei |
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Texas Instruments |
2-A High Efficiency Synchronous Buck Converter •1 Up to 95% Efficiency • Low RDS(ON) Switches 100 mΩ / 60 mΩ • 2.5-V to 5.5-V Input Voltage Range • Adjustable Output Voltage from 0.6 V to VIN • Power Save Mode for Light Load Efficiency • 100% Duty Cycle for Lowest Dropout • 35-µA Operating Quiesc |
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Texas Instruments |
1-A High Efficiency Synchronous Buck Converter •1 Up to 95% Efficiency • Low RDS(ON) Switches 150 mΩ / 100 mΩ • 2.5-V to 5.5-V Input Voltage Range • Adjustable Output Voltage from 0.6 V to VIN • Power Save Mode for Light Load Efficiency • 100% Duty Cycle for Lowest Dropout • 35-µA Operating Quies |
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Texas Instruments |
5.6-W Class-D Mono Audio Amplifier •1 Ultra Low-Noise Mono Boosted Class-D Amplifier – 5.6 W at 1% THD+N and 6.9 W at 10% THD+N into 4-Ω Load from 4.2-V Supply – 3.7 W at 1% THD+N and 4.5 W at 10% THD+N into 8-Ω Load from 4.2-V Supply • Output Noise for DAC + Class-D(ICN) is 16.2 μV • |
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ETC |
LED flashlight controller |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
HMS30C7202 32-bit ARM7TDMI RISC static CMOS CPU core : Running up to 70 MHz 8Kbytes combined instruction/data cache Memory management unit Supports Little Endian operating system 2Kbytes SRAM for internal buffer memory On-chip peripherals with indiv |
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ETC |
HMS30C7202 32-bit ARM7TDMI RISC static CMOS CPU core : Running up to 70 MHz 8Kbytes combined instruction/data cache Memory management unit Supports Little Endian operating system 2Kbytes SRAM for internal buffer memory On-chip peripherals with indiv |
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Texas Instruments |
256-Channel Analog Front-End 1 •23 256 Channels • On-Chip, 14-Bit ADC • High Performance: – Noise: 758 electronRMS (eRMS) with 28-pF Sensor Capacitor in 1.2-pC Range – Integral Nonlinearity: ±1.25 LSB with Internal 14-Bit ADC – Minimum Scan Time: – Normal Mode: 37.9 µs, Internal |
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Texas Instruments |
Turbo CAN Transceivers for Functional Safety 1 Features •1 Meets the Requirements of ISO11898-2 • Turbo CAN: – Short and Symmetrical Propagation Delay Times and Fast Loop Times for Enhanced Timing Margin – Higher Data Rates in CAN Networks • I/O Voltage Range Supports 3.3 |
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Texas Instruments |
256-Taps Dual Channel Digital Potentiometer •1 Two Potentiometers With 256-Position Resolution • Non-Volatile Memory Stores Wiper Settings • 10-kΩ End-to-End Resistance (TPL0202-10) • Fast Power-Up Response Time: <100 µs • ±1 LSB INL, ±0.5 LSB DNL (Voltage-Divider Mode) • 12 ppm/°C Ratiometric |
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Desde 2024. D4U Semiconductor.
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