| No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Cypress Semiconductor |
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs • High-speed, low-power, first-in, first-out (FIFO) memories • 64 x 9 (CY7C4421V) • 256 x 9 (CY7C4201V) • 512 x 9 (CY7C4211V) • 1K x 9 (CY7C4221V) • 2K x 9 (CY7C4231V) • 4K x 9 (CY7C4241V) • 8K x 9 (CY7C4251V) • High-speed 66-MHz operation (15-ns rea |
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Cypress Semiconductor |
32K/64Kx18 Deep Sync FIFOs • High-speed, low-power, first-in first-out (FIFO) memories • 32K x 18 (CY7C4275) • 64K x 18 (CY7C4285) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — ICC=50 mA • • • • • • • • • |
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Cypress Semiconductor |
256K (32K x 8) Static RAM ■ Temperature range ❐ –40 °C to 85 °C ■ Pin and function compatible with CY7C199C ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0 V data retention ■ Automatic power-down when deselecte |
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Cypress Semiconductor |
36-Mbit (1M x 36) Pipelined Sync SRAM ■ Supports bus operation up to 250 MHz ■ Available speed grade is 250 MHz ■ Registered inputs and outputs for pipelined operation ■ 2.5-V core power supply ■ 2.5-V I/O power supply ■ Fast clock-to-output times ❐ 2.5 ns (for 250-MHz device) ■ Provide |
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Cypress Semiconductor |
USE ULTRA37000TM FOR ALL NEW DESIGNS(128-Macrocell MAX EPLD) • 128 macrocells in eight logic array blocks (LABs) • 20 dedicated inputs, up to 64 bidirectional I/O pins • Programmable interconnect array • 0.8-micron double-metal CMOS EPROM technology • Available in 84-pin CLCC, PLCC, and 100-pin PGA, PQFP The 1 |
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Cypress Semiconductor |
1-Mbit (1 M x 1) Static RAM ■ Pin- and function-compatible with CY7C107B/CY7C1007B ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA @ 10 ns ■ Low complementary metal oxide semiconductor (CMOS) standby power ❐ ISB2 = 3 mA ■ 2.0 V data retention ■ Automatic power-down |
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Cypress Semiconductor |
High-Speed Multi-Phase PLL Clock Buffer ■ 500 ps max Total Timing Budget (TTB™) window ■ 24 MHz –200 MHz input and Output Operation ■ Low Output-output skew <200 ps ■ 10 + 1 LVTTL outputs driving 50 terminated lines ■ Dedicated feedback output ■ Phase adjustments in 625 ps/1300 ps steps u |
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Cypress Semiconductor |
72-Mbit QDR II+ SRAM Four-Word Burst Architecture ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 550 MHz clock for high bandwidth ■ Four-word burst for reducing address bus frequency ■ Double data rate (DDR) interfaces on both read and write ports (data transfe |
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Cypress Semiconductor |
2K x 8 Reprogrammable PROM • Windowed for reprogrammability • CMOS for optimum speed/power • High speed — 20 ns (Commercial) — 35 ns (Military) • Low power — 660 mW (Commercial and Military) • Low standby power — 220 mW (Commercial and Military) • EPROM technology 100% program |
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Cypress Semiconductor |
18-Mbit Burst of 4 Pipelined SRAM Functional Description • Separate independent Read and Write data ports • Supports concurrent transactions • 167-MHz clock for high bandwidth • 2.5 ns Clock-to-Valid access time • 4-Word Burst for reducing the address bus frequency • Double Data Ra |
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Cypress Semiconductor |
High-Speed USB Peripheral Controller ■ USB 2.0 USB IF Hi-Speed certified (TID # 40460272) ■ Single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051 microprocessor ■ Fit-, form-, and function-compatible with the FX2 ❐ Pin-compatible0 ❐ Object-code-compatible ❐ Functional |
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Cypress Semiconductor |
Low Voltage Microcontroller ■ Powerful Harvard Architecture processor ❐ M8C processor speeds running up to 24 MHz ❐ Low power at high processing speeds ❐ Interrupt controller ❐ 1.71 V to 3.6 V operating voltage ❐ Commercial temperature range: 0 °C to +70 °C ■ Flexible on-chip m |
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Cypress Semiconductor |
36-Mbit (1 M x 36/2 M x 18) Pipelined SRAM ■ Pin-compatible and functionally equivalent to ZBT™ ■ Supports 250-MHz bus operations with zero wait states ❐ Available speed grades is 250 MHz ■ Internally self-timed output buffer control to eliminate the need to use asynchronous OE ■ Fully regist |
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Cypress Semiconductor |
1-Mbit (64 K x 16) Static RAM ■ Temperature ranges ❐ Commercial: 0 °C to 70 °C ❐ Industrial: –40 °C to 85 °C ❐ Automotive-A: –40 °C to 85 °C ❐ Automotive-E: –40 °C to 125 °C ■ High speed ❐ tAA = 15 ns (Automotive) ■ Complementary metal oxide semiconductor (CMOS) for optimum speed |
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Cypress Semiconductor |
16-Mbit (1M x 16) Static RAM ■ High speed ❐ tAA = 10 ns ■ Embedded error-correcting code (ECC) for single-bit error correction ■ Low active power ❐ ICC = 90 mA typical ■ Low CMOS standby power ❐ ISB2 = 20 mA typical ■ Operating voltages of 3.3 ± 0.3 V ■ 1.0 V data retention ■ Tr |
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Cypress Semiconductor |
16-Mbit (1M x 16) Static RAM ■ High speed ❐ tAA = 10 ns ■ Embedded error-correcting code (ECC) for single-bit error correction ■ Low active power ❐ ICC = 90 mA typical ■ Low CMOS standby power ❐ ISB2 = 20 mA typical ■ Operating voltages of 3.3 ± 0.3 V ■ 1.0 V data retention ■ Tr |
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Cypress Semiconductor |
Low-speed USB Peripheral Controller ..................................................................................................................................... 5 2.0 FUNCTIONAL OVERVIEW .......................................................................................... |
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Cypress Semiconductor |
18-Mbit Burst of Two-Pipelined SRAM ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 167 MHz clock for high bandwidth ❐ 2.5 ns clock-to-valid access time ■ Two word burst on all accesses ■ Double data rate (DDR) interfaces on both read and write por |
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Cypress Semiconductor |
1.8V Synchronous Pipelined SRAM ■ Separate independent read and write data ports ❐ Supports concurrent transactions ■ 250 MHz clock for high bandwidth ■ 2-word burst on all accesses ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 500 MHz) at 2 |
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Cypress Semiconductor |
(CY7B9910 / CY7B9920) Low Skew Clock Buffer • • • • • • • • • All outputs skew <100 ps typical (250 max.) 15- to 80-MHz output operation Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines Low operating current 24-pin SOIC package Jitter: <200 ps peak to peak, |
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Desde 2024. D4U Semiconductor.
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