No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Altera Corporation |
(EPMxxxx) JTAG & In-System Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 –2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 –1 Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . |
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Altera Corporation |
Programmable Logic Device .. ■ ■ ■ ■ ■ ■ ■ ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149 |
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Altera Corporation |
(EPMxxxx) JTAG & In-System Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 –2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 –1 Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . |
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Altera Corporation |
Max 9000(a) Programmable Logic Device Family (6k Gates) .. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Tes |
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Altera Corporation |
Max 9000(a) Programmable Logic Device Family (6k Gates) .. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Tes |
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Altera Corporation |
(EPM7000B) Programmable Logic Device .. ■ ■ High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) – Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device famil |
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Altera Corporation |
(EPM7000B) Programmable Logic Device .. ■ ■ High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) – Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device famil |
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Altera Corporation |
EPM7032STC .. ■ ■ ■ www.DataSheet4U.com ■ ■ ■ ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Grou |
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Altera |
Programmable Logic .. ■ High –performance, low –cost CMOS EEPROM –based programmable logic devices (PLDs) built on a MAX® architecture (see Table 1) ■ 3.3-V in-system programmability (ISP) through the built –in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface wit |
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Altera |
(EPM5016 - EPM5192) High Speed High Density MAX 5000 Devices |
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Altera |
Programmable Logic .. s Advanced Multiple Array MatriX (MAX) 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays s Complete family of high-performance, erasable CMOS EPROM EPLDs for designs ranging from fast 28 |
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Altera |
High Performance 160-Macrocell Device |
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Altera |
Programmable Logic .. f ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture ■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in |
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Altera |
Programmable Logic .. f ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture ■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in |
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Altera Corporation |
Programmable Logic Device .. ■ ■ ■ ■ ■ ■ ■ ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149 |
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Altera Corporation |
Programmable Logic Device .. ■ ■ ■ ■ ■ ■ ■ ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149 |
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Altera Corporation |
Programmable Logic Device .. ■ ■ ■ ■ ■ ■ ■ ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149 |
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Altera Corporation |
Programmable Logic Device .. ■ ■ ■ ■ ■ ■ ■ ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149 |
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Altera Corporation |
(EPMxxxx) JTAG & In-System Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 –2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 –1 Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . |
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Altera Corporation |
(EPMxxxx) JTAG & In-System Programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 –2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 –1 Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . |
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