No. | parte # | Fabricante | Descripción | Hoja de Datos |
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Altera |
EPLD 24 Macrocell Device |
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Altera |
EPLD Classic |
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Altera |
EPLD Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s Device erasure and reprogramming with non-volatile EPROM configuration elements s Fast pin-to-pin logic delays as low as 10 ns |
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|
|
Altera |
EPLD Classic ® EPLD Family Data Sheet s Complete device family with logic densities of 300 to 900 usable gates (see Table 1) s Device erasure and reprogramming with non-volatile EPROM configuration elements s Fast pin-to-pin logic delays as low as 10 ns |
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