AEROFLEX UT8 Hoja de datos

No.	parte #	Fabricante	Descripción
1	UT8QNF8M8	Aeroflex Circuit Technology	64Mbit NOR Flash Memory  64Mbits organized as either 8M x 8-bits or 4M x16-bits  Fast 60ns read/write access time  Functionally compatible with traditional single power supply Flash devices  Simultaneous read/write operations  Flexible bank architecture  Single 3.3V p
2	UT8ER512K32	Aeroflex Circuit Technology	Monolithic 16M SRAM  20ns Read, 10ns Write maximum access times  Functionally compatible with traditional 512K x 32 SRAM devices  CMOS compatible input and output levels, three-state bidirectional data bus - I/O Voltage 3.3 volt, 1.8 volt core  Operational environme
3	UT8CR512K32	Aeroflex Circuit Technology	UT8CR512K32 16 Megabit SRAM 17ns maximum access time Asynchronous operation for compatibility with industrystandard 512K x 8 SRAMs CMOS compatible inputs and output levels, three-state bidirectional data bus - I/O Voltage 3.3 volts, 1.8 volt core Radiation performance -
4	UT80CRH196KDS	Aeroflex Circuit Technology	Microcontroller 20MHz 16-bit Microcontroller compatible with industry standard’s MCS-96 ISA - Register to Register Architecture - 1000 Byte Register RAM Three 8-bit I/O Ports On-board Interrupt Controller Three Pulse-Width Modulated Outputs High Speed I/O
5	UT8Q512K32E	Aeroflex Circuit Technology	16 Megabit RadTolerant SRAM MCM  25ns maximum (3.3 volt supply) address access time  MCM contains four (4) 512Kx8 industry-standard asynchronous SRAMs; the control architecture allows operation as 8, 16, 24 or 32-bit data width  TTL compatible inputs and output levels, three-sta
6	UT8R128K32	Aeroflex Circuit Technology	128K x 32 SRAM 15ns maximum access time Asynchronous operation, functionally compatible with industry-standard 128K x 32 SRAMs CMOS compatible inputs and output levels, three-state bidirectional data bus - I/O Voltage 3.3 volts, 1.8 volt core Operational en
7	UT8R512K8	Aeroflex Circuit Technology	512K x 8 SRAM 15ns maximum access time Asynchronous operation for compatibility with industry- standard 512K x 8 SRAMs CMOS compatible inputs and output levels, three-state bidirectional data bus - I/O Voltage 3.3 volts, 1.8 volt core Operational environme
8	UT8SP2M48	Aeroflex Circuit Technology	96Megabit Pipelined SSRAM  Synchronous SRAM organized as 2Meg words x 48bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 133MHz bus operations  Internally self-timed output buffer control eliminat
9	UT80C196	Aeroflex Circuit Technology	UT80C196KD Microcontroller q 20MHz 16-bit Microcontroller compatible with Industry Standard’s MCS-96 ISA - Register to Register Architecture - 1000 Byte Register RAM q Three 8-bit I/O Ports q On-board Interrupt Controller q Three Pulse-Width Modulated Outputs q High Speed I/O
10	UT8Q1024K8	Aeroflex Circuit Technology	high-performance 1M byte (8Mbit) CMOS static RAM 25ns maximum (3.3 volt supply) address access time Dual cavity package contains two (2) 512K x 8 industrystandard asynchronous SRAMs; the control architecture allows operation as an 8-bit data width TTL compatible inputs and output levels, thre
11	UT80CRH196KD	AEROFLEX	20MHz 16-bit Microcontroller q 20MHz 16-bit Microcontroller compatible with industry standard’s MCS-96 ISA - Register to Register Architecture - 1000 Byte Register RAM q Three 8-bit I/O Ports q On-board Interrupt Controller q Three Pulse-Width Modulated Outputs q High Speed I/O
12	UT8Q512E	Aeroflex Circuit Technology	512K x 8 RadTol SRAM 20ns maximum (3.3 volt supply) address access time Asynchronous operation for compatibility with industry- standard 512K x 8 SRAMs TTL compatible inputs and output levels, three-state bidirectional data bus Operational environment: - Total do
13	UT8SF2M32	Aeroflex Circuit Technology	64Megabit Flow-thru SSRAM  Synchronous SRAM organized as 2Meg words x 32bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 80MHz bus operations  Internally self-timed output buffer control eliminate
14	UT8SF2M40	Aeroflex Circuit Technology	80Megabit Flow-thru SSRAM  Synchronous SRAM organized as 2Meg words x 40bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 80MHz bus operations  Internally self-timed output buffer control eliminate