A-Data Technology ADS Hoja de datos

No.	parte #	Fabricante	Descripción
1	ADS6616A4A	A-Data Technology	Synchronous DRAM •JEDEC standard LVTTL 3.3V power supply •MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,3,8,& full page) -Burst Type (sequential & Interleave) •4 banks operation •All inputs are sampled at the positive edge of the system
2	ADS7616A4A	A-Data Technology	Synchronous DRAM(2M X 16 Bit X 4 Banks) •JEDEC standard LVTTL 3.3V power supply •MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,4,8,& full page) -Burst Type (sequential & Interleave) •4 banks operation •All inputs are sampled at the positive edge of the system
3	ADS6632A4A	A-Data Technology	Synchronous DRAM •JEDEC standard LVTTL 3.3V power supply •MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,3,8,& full page) -Burst Type (sequential & Interleave) •4 banks operation •All inputs are sampled at the positive edge of the system
4	ADS8608A8A	A-Data Technology	Synchronous DRAM(8M X 8 Bit X 4 Banks)
5	ADS8616A8A	A-Data Technology	Synchronous DRAM(4M X 16 Bit X 4 Banks)
6	ADS8616A8A-75A	A-Data Technology	Synchronous DRAM(4M X 16 Bit X 4 Banks)
7	ADS4616A4A	A-Data Technology	Synchronous DRAM •Single 3.3V +/- 0.3V power supply •MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,4,8, & full page) -Burst Type (sequential & Interleave) •2 banks operation •All inputs are sampled at the positive edge of the system cloc
8	ADS6608A4A	A-Data Technology	Synchronous DRAM •JEDEC standard LVTTL 3.3V power supply •MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,4,8,& full page) -Burst Type (sequential & Interleave) •4 banks operation •All inputs are sampled at the positive edge of the system
9	ADS7608A4A	A-Data Technology	Synchronous DRAM(4M X 8 Bit X 4 Banks) •JEDEC standard LVTTL 3.3V power supply •MRS Cycle with address key programs -CAS Latency (2 & 3) -Burst Length (1,2,3,8,& full page) -Burst Type (sequential & Interleave) •4 banks operation •All inputs are sampled at the positive edge of the system
10	ADS8608A8A-75	A-Data Technology	Synchronous DRAM(8M X 8 Bit X 4 Banks)
11	ADS8608A8A-75A	A-Data Technology	Synchronous DRAM(8M X 8 Bit X 4 Banks)
12	ADS8616A8A-75	A-Data Technology	Synchronous DRAM(4M X 16 Bit X 4 Banks)