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SN74LS273 Octal D Flip-Flop

SN74LS273


SN74LS273
Part Number SN74LS273
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SN74LS273

Motorola
SN74LS273
Part Number SN74LS273
Manufacturer Motorola
Title OCTAL D FLIP-FLOP
Description The SN54 / 74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset. When the MR input is LOW, the Q outputs are LOW, independent of the other inputs. Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH .
Features L Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. ORDERING INFORMATION SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC TRUTH TABLE MR L H H CP X Dx X H L Qx L H L H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM 11 3 4 7 8 13 14 17 18 D0 D1 D2 D3 D4.

SN74LS273

Texas Instruments
SN74LS273
Part Number SN74LS273
Manufacturer Texas Instruments
Title OCTAL D-TYPE FLIP-FLOP
Description These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input. Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occ.
Features LS273. SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR SDLS090
  – OCTOBER 1976
  – REVISED MARCH 1988 SN54273, SN74LS273 . . . J OR W PACKAGE SN74273 . . . N PACKAGE SN74LS273 . . . DW OR N PACKAGE (TOP VIEW) CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK SN54LS273 . . . FK PACKAGE (TOP VIEW) 1D 1Q CLR.

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