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ICS93705 DDR Phase Lock Loop Zero Delay Clock Buffer Datasheet


ICS93705

Renesas
ICS93705

Part Number ICS93705
Manufacturer Renesas (https://www.renesas.com/)
Description Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Spread Spectrum tolerant inputs • 3.3V tolerant CLK_INT input Switching Characteristics: • PEAK - PEAK jitter (66MHz): <120ps • PEAK - PEAK jitter (>100MHz)...
Features
• Low skew, low jitter PLL clock driver
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• 3.3V tolerant CLK_INT input Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (66MHz):<120ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 450ps - 950ps
• DUTY CYCLE: 49% - 51% Pin Configuration GND CLKC0 CLKT0 VDD CLKT1 CLKC1 GND GND CLKC2 CLKT2 VDD SCLK CLK_INT N/C VDD AVDD AGND GND CLKC3 CLKT3 VDD...

Document Datasheet ICS93705 datasheet pdf (306.81KB)



ICS93705

Integrated Circuit Systems
ICS93705
Part Number ICS93705
Manufacturer Integrated Circuit Systems
Title DDR Phase Lock Loop Zero Delay Clock Buffer
Description Features: • Low skew, low jitter PLL clock driver • I2C for functional and output control • Feedback pins for input to output synchronization • Sp.
Features
• Low skew, low jitter PLL clock driver
• I2C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• 3.3V tolerant CLK_INT input Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
•.

Document ICS93705 datasheet pdf



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