DM74LS73A FLIP-FLOPS Datasheet, Distribuidor, stock y mejor precio

Part Number	DM74LS73A
Manufacturer	Fairchild Semiconductor
Title	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops
Description	This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the neg.
Features	uit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs CLR L H H H H H CLK X ↓ ↓ ↓ ↓ H J X L H L H X K X L L H H X Q0 Q L Q0 H L Toggle Q0 Outputs Q H Q0 L H H = HIGH Logic Level L = LOW Logic Le.

No.	Parte #	Fabricante	Descripción
1	DM74LS74A	National Semiconductor	Dual Positive-Edge-Triggered D Flip-Flops
2	DM74LS74A	Fairchild Semiconductor	Dual Positive-Edge-Triggered D Flip-Flops
3	DM74LS75	Fairchild Semiconductor	Quad Latch
4	DM74LS00	Fairchild Semiconductor	Quad 2-Input NAND Gate
5	DM74LS00	National Semiconductor	Quad 2-Input NAND Gates
6	DM74LS02	Fairchild Semiconductor	Quad 2-Input NOR Gate
7	DM74LS02	National Semiconductor	Quad 2-Input NOR Gates
8	DM74LS03	Fairchild Semiconductor	Quad 2-Input NAND Gates
9	DM74LS03	National Semiconductor	Quad 2-Input NAND Gates
10	DM74LS04	Fairchild Semiconductor	Hex Inverting Gates

DM74LS73A Datasheet. existencias, precio