| Part Number | 8540 |
| Manufacturer | Excel |
| Title | Numeric Displays |
| Description | ... |
| Features |
... |
| Document | 8540 datasheet pdf - 104.63KB |
| Part Number | 854S057B |
| Manufacturer | Renesas |
| Title | 4:1 or 2:1 LVDS Clock Multiplexer |
| Description | The 854S057B is a 4:1 or 2:1 LVDS Clock Multiplexer which can operate up to 2GHz. The PCLK, nPCLK pairs can accept most standard differential inpu. |
| Features |
• High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum out. |
| Document | 854S057B datasheet pdf |
| Part Number | 854S057B |
| Manufacturer | IDT |
| Title | 4:1 or 2:1 LVDS Clock Multiplexer |
| Description | The 854S057B is a 4:1 or 2:1 LVDS Clock Multiplexer which can operate up to 2GHz. The PCLK, nPCLK pairs can accept most standard differential inpu. |
| Features |
• High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four sele. |
| Document | 854S057B datasheet pdf |
| Part Number | 854S057 |
| Manufacturer | Renesas |
| Title | 4:1 or 2:1 LVDS Clock Multiplexer |
| Description | The 854S057 is a 4:1 or 2:1 LVDS Clock Multiplexer which can operate up to 2GHz. The PCLK, nPCLK pairs can accept most standard differential input. |
| Features |
• High speed differential multiplexer. The device can be configured as either a 4:1 or 2:1 multiplexer • One LVDS output pair • Four selectable PCLK, nPCLK inputs with internal termination • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum out. |
| Document | 854S057 datasheet pdf |
| Part Number | 854S01I |
| Manufacturer | Renesas |
| Title | 2:1 Differential-to-LVDS Multiplexer |
| Description | The 854S01I is a high performance 2:1 Differential-to-LVDS Multiplexer. The 854S01I can also perform differential translation because the differen. |
| Features |
• 2:1 LVDS MUX • One LVDS output pair • Two differential clock inputs can accept: LVPECL, LVDS, CML • Maximum input/output frequency: 2.5GHz • Translates LVCMOS/LVTTL input signals to LVDS levels by using a resistor bias network on nPCLK0, nPCLK1 • RMS additive phase jitter: 0.06ps (typical) • Propa. |
| Document | 854S01I datasheet pdf |
| Part Number | 854S006I |
| Manufacturer | IDT |
| Title | Differential-to-LVDS Fanout Buffer |
| Description | The 854S006I is a low skew, high perfor- mance 1-to-6 Differential-to-LVDS Fanout Buffer. The CLK, nCLK pair can accept most standard differential. |
| Features |
• Six differential LVDS outputs • One differential clock input pair • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 1.7GHz • Translates any single ended input signal to LVDS levels with resistor bias on nCLK input • Ou. |
| Document | 854S006I datasheet pdf |
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