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74LS241 Octal 3-STATE Buffer/Line Driver/Line Receiver

74LS241


74LS241
Part Number 74LS241
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74LS241

Motorola
74LS241
Part Number 74LS241
Manufacturer Motorola
Title OCTAL BUFFER/LINE DRIVER
Description OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS The SN54 / 74LS240, 241 and 244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. SN54/74LS240 SN54/74LS241 SN54/74LS244 .
Features XXXDW SOIC 1 1G 2 1A1 3 4 5 6 1A3 7 8 9 10 GND 2Y4 1A2 2Y3 2Y2 1A4 2Y1 SN54 / 74LS244 VCC 2G 20 19 1Y1 18 2A4 1Y2 17 16 2A3 15 1Y3 2A2 1Y4 14 13 12 2A1 11 1 1G 2 1A1 3 4 5 6 1A3 7 8 9 10 GND 2Y4 1A2 2Y3 2Y2 1A4 2Y1 FAST AND LS TTL DATA 5-387 SN54/74LS240
• SN54/74LS241
• SN54/74LS244 TRUTH TABLES SN54 / 74LS240 INPUTS OUTPUT 1G, 2G L L H D L H X H L (Z) 1G, 2G L L H D L H X L H (Z) .

74LS241

Hitachi Semiconductor
74LS241
Part Number 74LS241
Manufacturer Hitachi Semiconductor
Title Octal Buffers/Line Drivers/Line Receivers
Description Unit: mm 24.50 25.40 Max 20 11 7.00 Max 6.30 1 0.89 1.27 Max 10 1.30 2.54 Min 5.08 Max 7.62 0.51 Min 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.11 Hitachi Code JEDEC EIAJ Weight (reference value) DP-20N — Conforms 1.26 g Unit: mm 12.6 13 Max 20 11 1 10 5.5 0.80 Max 2.20 Max *0.
Features any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without .

74LS241

National Semiconductor
74LS241
Part Number 74LS241
Manufacturer National Semiconductor
Title Octal TRI-STATE Buffers/Line Drivers/Line Receivers
Description These buffers line drivers are designed to improve both the performance and PC board density of TRI-STATE buffers drivers employed as memory-address drivers clock drivers and bus-oriented transmitters receivers Featuring 400 mV of hysteresis at each low current PNP data line input they provide impro.
Features Y Y Y Y Y TRI-STATE outputs drive bus lines directly PNP inputs reduce DC loading on bus lines Hysteresis at data inputs improves noise margins Typical IOL (sink current) 54LS 12 mA 74LS 24 mA Typical IOH (source current) b 12 mA 54LS b 15 mA 74LS Typical propagation delay times Inverting 10 5 ns Noninverting 12 ns Typical enable disable time 18 ns Typical power dissipation (enabled) Inverting .

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