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| Part Number | 74F74 |
| Distributor | Stock | Price | Buy |
|---|
| Part Number | 74F74 |
| Manufacturer | Fairchild |
| Title | Dual D-Type Positive Edge-Triggered Flip-Flop |
| Description | The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the trans. |
| Features | Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS. |
| Part Number | 74F74 |
| Manufacturer | National |
| Title | Dual D-Type Positive Edge-Triggered Flip-Flop |
| Description | The ’F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary (Q Q) outputs Information at the input is transferred to the outputs on the positive edge of the clock pulse Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transit. |
| Features | Y Guaranteed 4000V minimum ESD protection Commercial 74F74PC Military Package Number N14A Package Description 14-Lead (0 300 Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0 150 Wide) Molded Small Outline JEDEC 14-Lead (0 300 Wide) Molded Small Outline EIAJ 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F74DM (Note 2) 74F74SC (Note 1) 74F74SJ (Note 1) 54F74FM. |
| Part Number | 74F74 |
| Manufacturer | Texas Instruments |
| Title | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS |
| Description | These devices contain two independent positiveedge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requi. |
| Features | racterized for operation from 0°C to 70°C. SN54F74 . . . J PACKAGE SN74F74 . . . D OR N PACKAGE (TOP VIEW) 1CLR 1 1D 2 1CLK 3 1PRE 4 1Q 5 1Q 6 GND 7 14 VCC 13 2CLR 12 2D 11 2CLK 10 2PRE 9 2Q 8 2Q SN54F74 . . . FK PACKAGE (TOP VIEW) 1D 1CLR NC VCC 2CLR 1CLK NC 1PRE NC 1Q 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 1Q GND NC 2Q 2Q FUNCTION TABLE INPUTS. |
similar datasheet
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | 74F711-1 |
Philips |
Multiplexers |
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| 2 | 74F711A |
Philips |
Multiplexers |
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| 3 | 74F712-1 |
Philips |
Multiplexers |
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| 4 | 74F712A |
Philips |
Multiplexers |
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| 5 | 74F723-1 |
Philips |
Quad 2-to-1 data selector multiplexer |
|
| 6 | 74F723A |
Philips |
Quad 2-to-1 data selector multiplexer |
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| 7 | 74F725-1 |
Philips |
Quad 2-to-1 data selector multiplexer |
|
| 8 | 74F725A |
Philips |
Quad 2-to-1 data selector multiplexer |
|
| 9 | 74F756 |
Philips |
Octal inverter buffer open-collector |
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| 10 | 74F757 |
Philips |
Octal inverter buffer open-collector |
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Desde 2024. D4U Semiconductor.
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