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P3204M2S5X2 |
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| Part Number | P3204M2S5X2 |
| Manufacturer | Apollo Memory System |
| Description | CLK I Clock DAT0 I/O/PP Data DAT1 I/O/PP Data DAT2 I/O/PP Data DAT3 I/O/PP Data DAT4 I/O/PP Data DAT5 I/O/PP Data DAT6 I/O/PP Data DAT7 I/O/PP Data CMD I/O/PP/OD Command/R... |
| Features |
• SDR Data sampling method • CLK frequency up to 200MHz Data rate – up to 200MB/s • 8-bits bus width supported • Single ended signaling with 4 selectable Drive Strength • Signaling levels of 1.8V • Tuning concept for Read Operations 1.3.2 HS200 System Block Diagram Figure 2 shows a typical HS200 Host and Device system. The host has a clock generator, which supplies CLK to the Device. For write operations, clock and data direction are the same, write data can be transferred synchronous with CLK, regardless of transmission line delay. For read operations, clock and data direction are opposite;... |
| Document |
 P3204M2S5X2 Data Sheet
PDF 2.15MB |
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