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A3S28D40JTP |
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| Part Number | A3S28D40JTP |
| Manufacturer | Zentel |
| Description | A3S28D40JTP is a 4-bank x 2,097,152-word x 16bit double data rate synchronous DRAM , with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is regi... |
| Features |
- VDD=VDDQ=2.5V+0.2V (-50) - Double data rate architecture ; two data transfers per clock cycle. - Bidirectional , data strobe (DQS) is transmitted/received with data - Differential clock input (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge ; - Data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0 , BA1 (Bank Address) - CAS latency - 2.0 / 2.5 / 3.0 (programmable) ;
Burst length - 2 / 4 / 8 (programmable) Burst type - Sequential / Interleave (programmable) - Auto Precharge / All... |
| Document |
 A3S28D40JTP Data Sheet
PDF 533.07KB |
| No. | Parte # | Fabricante | Descripción | Hoja de Datos |
|---|---|---|---|---|
| 1 | A3S28D40FTP |
Zentel |
128M Double Data Rate Synchronous DRAM |
|
| 2 | A3S28D30FTP |
Zentel |
128M Double Data Rate Synchronous DRAM |
|
| 3 | A3S12D30ETP |
Powerchip |
512Mb DDR SDRAM |
|
| 4 | A3S12D40ETP |
Powerchip |
512Mb DDR SDRAM |
|
| 5 | A3S56D30ETP |
Zentel |
(A3S56D30ETP / A3S56D40ETP) 256Mb DDR SDRAM |
|
| 6 | A3S56D30FTP |
Zentel |
256M Double Data Rate Synchronous DRAM |
|
Desde 2024. D4U Semiconductor.
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