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P3S56D40ETP |
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| Part Number | P3S56D40ETP |
| Manufacturer | Mitsubishi |
| Description | M2S56D20ATP is a 4-bank x 16,777,216-word x 4-bit, M2S56D30ATP is a 4-bank x 8,388,608-word x 8-bit, M2S56D40ATP is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 i... |
| Features |
- Vdd=Vddq=2.5V+0.2V - Double data rate architecture;
two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions with CLK transitions edges of DQS - Commands entered on each positive CLK edge; - data and data mask referenced to both edges of DQS - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst type- sequential / interleave (programmable) - Auto precharge / All bank precharge contro... |
| Document |
 P3S56D40ETP Data Sheet
PDF 815.69KB |
Desde 2024. D4U Semiconductor.
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