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IDTCSPT855 |
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| Part Number | IDTCSPT855 |
| Manufacturer | Integrated Device Technology |
| Description | The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y [0:3], Y [0:3]) and one d... |
| Features |
DESCRIPTION:
The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y [0:3], Y [0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a highimpedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20MH... |
| Document |
 IDTCSPT855 Data Sheet
PDF 105.40KB |
Similar Datasheet
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Desde 2024. D4U Semiconductor.
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