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HYB18T256400BCL |
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| Part Number | HYB18T256400BCL |
| Manufacturer | Qimonda |
| Description | All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). ... |
| Features |
The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality • DRAM organizations with 4, 8 and 16 data in/outputs • Auto-Precharge operation for read and write bursts • Double Data Rate architecture: two data transfers per • Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes • Programmable CAS Latency: 3, 4, 5 and 6 • Average Refresh Period 7.8 μs ... |
| Document |
 HYB18T256400BCL Data Sheet
PDF 4.11MB |
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Desde 2024. D4U Semiconductor.
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