HYB18T512160BF |
Part Number | HYB18T512160BF |
Manufacturer | Qimonda |
Description | latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 16-bit a... |
Features |
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and On • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality • DRAM organizations with 4 and 8 data in/outputs • Auto-Precharge operation for read and write bursts • Double-Data-Rate-Two architecture: two data transfers • Auto-Refresh, Self-Refresh and power saving Powerper clock cycle four internal banks for concurrent operation Down modes • Programmable CAS Latency: 3, 4, 5 and 6 • Average Refresh Period 7.8 µs a... |
Document |
HYB18T512160BF Data Sheet
PDF 3.73MB |
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